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MAX5742AUB Datasheet(PDF) 3 Page - Maxim Integrated Products |
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MAX5742AUB Datasheet(HTML) 3 Page - Maxim Integrated Products |
3 / 15 page 12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k Ω, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are VDD = +5V, TA = +25°C.) TIMING CHARACTERISTICS (VDD = 2.7V to 5.5V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.) Note 1: DC specifications are tested without output loads. Note 2: Linearity guaranteed from code 115 to code 3981. Note 3: Limited with test conditions. Note 4: Offset and gain error limit the FSR. Note 5: Guaranteed by design. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS) Input High Voltage VIH VDD = +3V, +5V 0.7 x VDD V Input Low Voltage VIL VDD = +3V, +5V 0.3 x VDD V Input Leakage Current IIN Digital inputs = 0 or VDD ±0.1 ±1µA Input Capacitance CIN 5pF DYNAMIC PERFORMANCE Voltage Output Slew Rate SR 0.5 V/µs Voltage Output Settling Time 400 hex to C00 hex (Note 5) 4 10 µs Digital Feedthrough Any digital inputs from 0 to VDD 0.1 nV-s Digital-Analog Glitch Impulse Major carry transition (code 7FF hex to code 800 hex) 12 nV-s DAC-to-DAC Crosstalk 2.4 nV-s POWER REQUIREMENTS Supply-Voltage Range VDD 2.7 5.5 V All digital inputs at 0 or VDD = 3.6V 229 395 Supply Current with No Load IDD All digital inputs at 0 or VDD = 5.5V 271 420 µA Power-Down Supply Current IDDPD All digital inputs at 0 or VDD = 5.5V 0.29 1 µA PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Clock Frequency f SCLK 0 20 MHz SCLK Pulse Width High tCH 25 ns SCLK Pulse Width Low tCL 25 ns CS Fall to SCLK Rise Setup Time tCSS 10 ns SCLK Fall to CS Rise Setup Time tCSH 10 ns DIN to SCLK Fall Setup Time tDS 15 ns DIN to SCLK Fall Hold Time tDH 0ns CS Pulse Width High tCSW 80 ns |
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