MAX550AEUA datasheet(3/16 Pages) MAXIM

Part #	MAX550AEUA

Description	2.5V to 5.5V, Low-Power, Single/Dual, 8-Bit Voltage-Output DACs in 關MAX Package

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Manufacturer	MAXIM [Maxim Integrated Products]

Direct Link	https://www.maximintegrated.com/en.html

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+2.5V to +5.5V, Low-Power, Single/Dual,

8-Bit Voltage-Output DACs in µMAX Package

_______________________________________________________________________________________

3

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C)

TIMING CHARACTERISTICS

(VDD = +2.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Digital inputs switching from 0V to VDD.) (Figure 3) (Note 4)

Note 1: Cold temperature specifications (to -40°C) guaranteed by design using six sigma design limits.

Note 2: Worst-case input resistance at REF occurs at DAC code 55 hex.

Note 3: Worst-case reference input current occurs at DAC code 55 hex.

Note 4: Guaranteed by design. Not production tested.

Note 5: IDD measured with DACs loaded with worst-case DAC code 55 hex.

CS = high, all digital inputs from 0V to VDD

CL = 20pF

To ±1/2LSB, CL = 20pF

V/µs

3.1

µs

1.4

Voltage-Output Settling Time

4

CONDITIONS

50

nV-sec

Digital Feedthrough and

Crosstalk

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

Voltage-Output Slew Rate

CL = 20pF

µs

Wake-Up Time at Power-Up

4

VDD = 2.5V

VDD = 5.5V

Supply Voltage Range

Outputs unloaded, all inputs = GND or VDD

VDD

V

2.5

5.5

Supply Current

(MAX549A/MAX550A)

Outputs unloaded,

all inputs = GND or

VDD (Note 5)

µA

330

550

IDD

Supply Current (MAX548A)

Outputs unloaded, all inputs = GND or VDD;

VDD = 5.5V

IDD

µA

0.3

10

VDD = 5.5V

VDD = 2.5V

Shutdown Current

Shutdown mode

µA

0.3

150

250

80

50

SCLK Period

tCP

CS High to LDAC Low

ns

tCSLD

ns

MAX548A/MAX550A only

5

VDD High to CS Low

µs

50

LDAC Pulse Width Low

tLDAC

ns

MAX548A/MAX550A only

40

CS Pulse Width High

tCSW

ns

20

tCSH1

ns

VDD = 5.5V

10

30

tDH

CS High to SCLK High Setup

ns

tCSS1

ns

10

Delay, SCLK High to CS High

VDD = 2.5V

VDD = 5.5V

30

CS Low to SCLK High Setup

tCSS0

ns

30

DIN to SCLK High Setup

tDS

ns

0

DIN to SCLK High Hold

VDD = 2.5V

40

SCLK Pulse Width Low

tCL

ns

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

CONDITIONS

40

SCLK Pulse Width High

tCH

ns

DYNAMIC PERFORMANCE

POWER SUPPLIES

10

SCLK High to CS Low Hold

tCSH0

ns

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