2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

4

_______________________________________________________________________________________

TIMING CHARACTERISTICS (continued)

Note 1:

or equal to the maximum offset specification to code FF hex (full scale). See

DAC Linearity and Voltage Offset section.

Note 2:

other DAC’s codes to 00 hex.

Note 3:

Note 4:

Guaranteed by design, not production tested.

Note 5:

Output settling time is measured from the 50% point of the rising edge of

Note 6:

Digital crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other

DAC.

Note 7:

If

Note 8:

Note 9:

CS Rise to SCLK Rise Setup

Time

50

ns

SCLK Rise to

CS Fall Delay

50

ns

MAX533M

MAX533M

40

40

MAX533C/E

MAX533C/E

SCLK Fall to DOUT Valid

Propagation Delay (Note 10)

250

ns

MAX533M

210

MAX533C/E

SCLK Rise to DOUT Valid

Propagation Delay (Note 9)

230

ns

MAX533M

200

MAX533C/E

40

CS Fall to SCLK Rise Setup

Time

50

40

ns

SCLK Pulse Width Low

50

ns

MAX533C/E

MAX533M

MAX533C/E

MAX533M

40

SCLK Pulse Width High

50

ns

MAX533C/E

MAX533M

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

SERIAL-INTERFACE TIMING

10

SCLK Clock Frequency (Note 8)

8.3

MHz

SCLK Rise to

CS Rise Hold Time

0

ns

40

DIN to SCLK Rise to Setup Time

50

DIN to SCLK Rise to Hold Time

0

ns

CONDITIONS

MAX533C/E

MAX533M

MAX533C/E

MAX533M