 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
IDT8T49N366I Datasheet(PDF) 7 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
IDT8T49N366I Datasheet(HTML) 7 Page - Integrated Device Technology |
|
|
7 / 36 page  IDT8T49N366AASGI REVISION A JUNE 28, 2013 7 ©2013 Integrated Device Technology, Inc. IDT8T49N366I Data Sheet FEMTOCLOCK® NG TRIPLE UNIVERSAL FREQUENCY TRANSLATORTM Frequency Synthesizer Mode This mode of operation allows an arbitrary output frequency to be generated from external REFCLK input. For improved phase noise performance, the REFCLK input frequency is doubled. As can be seen from the block diagram in Figure 1, only the upper feedback loop is used in this mode of operation. It is recommended that CLK0 and CLK1 be left unused in this mode of operation. The upper feedback loop supports a delta-sigma fractional feedback divider. This allows the VCO operating frequency to be a non-integer multiple of the REFCLK frequency. By using an integer multiple only, lower phase noise jitter on the output can be achieved, however the use of the delta-sigma divider logic will provide excellent performance on the output if a fractional divisor is used. Figure 1. Frequency Synthesizer Mode Block Diagram High-Bandwidth Frequency Translator Mode This mode of operation is used to translate one of two input clocks of the same nominal frequency into an output frequency. As can be seen from the block diagram in Figure 2, similarly to the Frequency Synthesizer mode, only the upper feedback loop is used. Figure 2. High Bandwidth Frequency Translator Mode Block Diagram The input reference frequency range is now extended up to 710MHz. A pre-divider stage P is needed to keep the operating frequencies at the phase detector within limits. Low-Bandwidth Frequency Translator Mode As can be seen from the block diagram in Figure 3, this mode involves two PLL loops. The lower loop with the large integer dividers is the low bandwidth loop and it sets the output-to-input frequency translation ratio.This loop drives the upper DCXO loop (digitally controlled crystal oscillator) via an analog-digital converter. Figure 3. Low Bandwidth Frequency Translator Mode Block Diagram The phase detector of the lower loop is designed to work with frequencies in the 8kHz - 16kHz range. The pre-divider stage is used to scale down the input frequency by an integer value to achieve a frequency in this range. By dividing down the fed-back VCO operating frequency by the integer divider M1[18:0] to as close as possible to the same frequency, exact output frequency translations can be achieved. Alarm Conditions & Status Bits Each PLL of IDT8T49N366I monitors a number of conditions and reports their status via both output pins and/or register bits. All alarms will behave as indicated below in all modes of operation, but some of the conditions monitored have no valid meaning in some operating modes. For example, the status of CLK0BADx, CLK1BADx and CLK_ACTIVEx are not relevant in Frequency Synthesizer mode. The outputs will still be active and it is left to the user to determine which to monitor and how to respond to them based on the known operating mode. CLK_ACTIVEx - indicates which input clock reference is being used to derive the output frequency. LOCKx - This status is asserted on the pin & register bit when the PLL is locked to the appropriate input reference for the chosen mode of operation. The status bit will not assert until frequency lock has been achieved, but will de-assert once lock is lost. REFBAD - indicates if valid edges are being received on the REFCLK input. Detection is performed by comparing the input to the feedback signal at the upper loop’s Phase / Frequency Detector (PFD). If three edges are received on the feedback without an edge on the REFCLK input, the REFBAD alarm is asserted in register bit. Once an edge is detected on the REFCLK input, the alarm is immediately deasserted. |
Similar Part No. - IDT8T49N366I |
|
Similar Description - IDT8T49N366I |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
