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IDT8T49N222I Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT8T49N222I Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 40 page IDT8T49N222BNLGI REVISION A MAY 13, 2013 6 ©2013 Integrated Device Technology, Inc. IDT8T49N222I Data Sheet FemtoClock® NG Universal Frequency Translator Below are some example configurations for some common frequency combinations. Please use the IDT Configuration SW or consult with IDT to select other options. Table 3B. Common Frequency Combination Examples Frequency Synthesizer Mode This mode of operation allows an arbitrary output frequency to be generated from a fundamental mode crystal input. For improved phase noise performance, the crystal input frequency may be dou- bled. As can be seen from the block diagram in Figure 1, only the up- per feedback loop is used in this mode of operation. It is recommend- ed that CLK0 and CLK1 be left unused in this mode of operation. The upper feedback loop supports a delta-sigma fractional feedback divider. This allows the VCO operating frequency to be a non-integer multiple of the crystal frequency. By using an integer multiple only, lower phase noise jitter on the output can be achieved, however the use of the delta-sigma divider logic will provide excellent perfor- mance on the output if a fractional divisor is used. Figure 1. Frequency Synthesizer Mode Block Diagram High-Bandwidth Frequency Translator Mode This mode of operation is used to translate one of two input clocks of the same nominal frequency into an output frequency with little jitter attenuation. As can be seen from the block diagram in Figure 2, similarly to the Frequency Synthesizer mode, only the upper feedback loop is used. Figure 2. High Bandwidth Frequency Translator Mode Block Diagram Output Frequency (MHz) Output Divider Ratio VCO Operating Frequency (MHz) 125 15 1875 156.25 12 25 75 1875 156.25 12 25 80 2000 125 16 155.52 12 1866.24 622.08 3 19.44 96 1866.24 622.08 3 161.1328125 12 1933.59375 644.53125 3 156.25 12 1875 625 3 122.88 20 2457.6 614.4 4 245.76 10 2457.6 614.4 4 30.72 80 2457.6 614.4 4 153.6 16 2457.6 614.4 4 15.36 144 2211.84 737.28 3 125 16 2000 133.3333 15 32.76 60 1965.6 131.04 15 26.5625 80 2125 212.5 10 106.25 18 1912.5 318.75 6 LOCK_IND XTALBAD Register Set Global Registers Control Logic SCLK, S_A0, S_A1 SDATA POR Status Indicators PD/LF ÷M_INT [7:0] ÷M_FRAC [17:0] PLL_BYPASS OSC XTAL_IN XTAL_OUT FemtoClock® NG VCO XTAL Feedback Divider 1 0 x2 ÷N0[7:0] Output Divider Q0 OE0 Q1 OE1 nQ0 nQ1 ÷N1[7:0] ÷P[16:0] CLK0 CLK1 CLK_SEL LOCK_IND CLK0BAD CLK1BAD CLK_ACTIVE Register Set Global Registers Control Logic SCLK, S_A0, S_A1 SDATA POR HOLDOVER Status Indicators nCLK1 nCLK0 0 1 PD/LF ÷M_INT [7:0] ÷M_FRAC [17:0] PLL_BYPASS FemtoClock® NG VCO Feedback Divider 1 0 ÷N0[7:0] Output Divider Q0 OE0 Q1 OE1 nQ0 nQ1 ÷N1[7:0] 0 1 0 1 |
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