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MAX5253BCAP Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX5253BCAP Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 16 page Figure 5 shows the serial-interface timing requirements. The chip-select pin ( CS) must be low to enable the DAC’s serial interface. When CS is high, the interface control circuitry is disabled. CS must go low at least tCSS before the rising serial clock (SCLK) edge to prop- erly clock in the first bit. When CS is low, data is clocked into the internal shift register via the serial-data input pin (DIN) on SCLK’s rising edge. The maximum guaranteed clock frequency is 10MHz. Data is latched into the appropriate MAX5253 input/DAC registers on CS’s rising edge. The programming command Load-All-DACs-From-Shift- Register allows all input and DAC registers to be simul- taneously loaded with the same digital code from the input shift register. The no operation (NOP) command leaves the register contents unaffected and is useful when the MAX5253 is configured in a daisy chain (see the Daisy Chaining Devices section). The command to change the clock edge on which serial data is shifted out of DOUT also loads data from all input registers to their respective DAC registers. Serial-Data Output (DOUT) The serial-data output, DOUT, is the internal shift regis- ter’s output. The MAX5253 can be programmed so that data is clocked out of DOUT on SCLK’s rising edge (Mode 1) or falling edge (Mode 0). In Mode 0, output data at DOUT lags input data at DIN by 16.5 clock cycles, maintaining compatibility with Microwire, SPI/QSPI, and other serial interfaces. In Mode 1, output data lags input data by 16 clock cycles. On power-up, DOUT defaults to Mode 0 timing. User-Programmable Logic Output (UPO) The user-programmable logic output, UPO, allows an external device to be controlled via the MAX5253 serial interface (Table 1). +3V, Quad, 12-Bit Voltage-Output DAC with Serial Interface 10 ______________________________________________________________________________________ Table 1. Serial-Interface Programming Commands 00 No operation (NOP) to DAC registers 00 11 UPO goes low (default) Enter shutdown mode (provided PDL = 1) 10 Load all DAC registers from shift register (exit shutdown mode). Load input register A; DAC registers unchanged. Load input register B; DAC registers unchanged. Load input register C; DAC registers unchanged. Load input register D; DAC registers unchanged. Load input register A; all DAC registers updated. Load input register B; all DAC registers updated. Load input register C; all DAC registers updated. Load input register D; all DAC registers updated. 01 01 00 01 10 11 00 01 10 11 Update all DAC registers from their respective input registers (exit shutdown mode). UPO goes high 00 10 00 00 00 10 01 01 01 01 11 11 11 11 XXXXXXXXXXXX 16-BIT SERIAL WORD XXXXXXXXXXXX XXXXXXXXXXXX 12-bit DAC data XXXXXXXXXXXX XXXXXXXXXXXX 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 10 XXXXXXXXXXXX Mode 0, DOUT clocked out on SCLK’s falling edge. All DAC registers updated (default). XXXXXXXXXXXX 11 Mode 1, DOUT clocked out on SCLK’s rising edge. All DAC registers updated. 10 10 “X” = Don’t care A1 A0 C1 C0 D11.................D0 MSB LSB FUNCTION |
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