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8V44N4614 Datasheet(PDF) 11 Page - Integrated Device Technology |
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8V44N4614 Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 31 page 8V44N4614 DATA SHEET REVISION 1 02/25/15 11 FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER Divider Control Register Register Register Bit D7 1 P1 P0 NC1 NC0 NB1 NB0 NA1 NA0 LVCMOS Output Control Register Table 4B. Divider Control Register Bit Allocations D6 D5 D4 D3 D2 D1 D0 Table 4C. Divider Control Register Function Descriptions Bits Name Factory Default Function Nm[1:0] Output Divider Setting NA = 01 NB = 11 NC = 10 These bits control the selection of the divider N for the output clock: 00 ÷16 01 ÷20 10 ÷25 11 ÷100 P[1:0] PLL Pre-Divider Setting P = 11 These bits control the selection of the input pre-divider P: 00 ÷1 01 ÷2 10 ÷4 11 ÷8 m = Output bank A, B, C Table 4D. LVCMOS Output Control Register Bit Allocations Register Register Bit D7 D6 D5 D4 D3 D2 D1 D0 2 INVC1 INVC0 INVB3 INVB2 INVB1 INVB0 INVA4 INVA3 3 INVC3 INVC2 Reserved ENA_QA4 ENA_QA3 ENA_QA2 ENA_QA1 ENA_QA0 Table 4E. LVCMOS Output Control Register Function Descriptions Bits Name Factory Default Function INVn Output Phase Inversion Reg 2: 1010 1010 Reg 3: 1000 1101 0 = Qn output phase is normal (0°) 1 = Qn output phase is inverted (180°) |
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