Low-Power, Serial, 12-Bit DACs with

Force/Sense Voltage Output

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11

The MAX5175/MAX5177 accept one 16-bit packet or

two 8-bit packets sent while CS remains low. The

devices allow the following to be configured:

• Clock edge on which serial data output (DOUT) is

clocked out

• State of the user-programmable logic output

• Reset state.

Specific commands for setting these are shown in

Table 1.

The general timing diagram in Figure 4 illustrates how

the MAX5175/MAX5177 acquire data. CS must go low

(SCLK). With CS low, data is clocked into the register

on the rising edge of SCLK. The maximum serial clock

frequency guaranteed for proper operation is 10MHz

for the MAX5175 and 6MHz for the MAX5177. See

Figure 5 for a detailed timing diagram of the serial inter-

face.

Table 1. Serial-Interface Programming Commands

Load input register; DAC registers are updated (start up DAC with

new data).

1

0

Load input register; DAC registers are unchanged.

0

0

12-bit DAC data

12-bit DAC data

00

00

16-BIT SERIAL WORD

D11..................D0

S1, S0

C1

FUNCTION

C0

No operation (NOP).

1

1

0 0 x x xxxx xxxx

xxxx xxxx xxxx

xx

xx

Update DAC register from input register (start up DAC with data

previously stored in the input registers).

0

1

UPO goes low (default).

1

1

1 0 0 x xxxx xxxx

0 1 x x xxxx xxxx

xx

xx

Mode 1, DOUT clocked out on SCLK’s rising edge.

1

1

1 1 0 x xxxx xxxx

1 0 1 x xxxx xxxx

xx

xx

UPO goes high.

1

1

Shut down DAC (provided PDL = 1).

1

1

Mode 0, DOUT clocked out on SCLK’s falling edge (default).

1

1

1 1 1 x xxxx xxxx

xx

DIN

SCLK

CS

MOSI

SCK

I/O

MAX5175

MAX5177

MICROWIRE

PORT

SS

+5V

CPOL = 0, CPHA = 0

Figure 2. Connections for SPI/QSPI Standards

SCLK

DIN

CS

SK

SO

I/O

SPI/QSPI

PORT

CPOL = 0, CPHA = 0

MAX5175

MAX5177

Figure 3. Connections for MICROWIRE