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8T49N241 Datasheet(PDF) 8 Page - Integrated Device Technology |
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8T49N241 Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 64 page  FEMTOCLOCK®NG UNIVERSAL FREQUENCY TRANSLATOR 8 REVISION 1 08/07/15 8T49N241 DATA SHEET While the PLL is in holdover, its frequency offset is now relative to the crystal input and so the output clocks will be tracing their accuracy to the local oscillator or crystal. At some point in time, depending on the stability & accuracy of that source, the clock(s) will have drifted outside of the limits of the holdover state and be considered to be in a free-run state. Since this borderline is defined outside the PLL and dictated by the accuracy and stability of the external local crystal or oscillator, the 8T49N241 cannot know or influence when that transition occurs. Input to Output Clock Frequency The 8T49N241 is designed to accept any frequency within its input range and generate four different output frequencies that are independent from the input frequencies and from each other. The internal architecture of the device ensures that most translations will result in the exact output frequency specified. Please contact IDT for configuration software or other assistance in determining if a desired configuration will be supported exactly. Synthesizer Mode Operation The device may act as a frequency synthesizer with the PLL generating its operating frequency from just the crystal input. By setting the SYN_MODE register bit and setting the STATE[1:0] field to Freerun, no input clock references are required to generate the desired output frequencies. When operating as a synthesizer, the precision of the output frequency will be < 1ppb for any supported configuration. Loop Filter and Bandwidth The 8T49N241 uses one external capacitor of fixed value to support its loop bandwidth. When operating in Synthesizer mode a fixed loop bandwidth of approximately 200kHz is provided. When not operating as a synthesizer, the 8T49N241 will support a range of loop bandwidths: 0.2Hz, 0.4Hz, 0.8Hz, 1.6Hz, 3.2Hz, 6.4Hz, 12Hz, 25Hz, 50Hz, 100Hz, 200Hz, 400Hz, 800Hz, 1.6kHz or 6.4kHz. The device supports two different loop bandwidth settings: acquisition and locked. These loop bandwidths are selected from the list of options described above. If enabled, the acquisition bandwidth is used while lock is being acquired to allow the PLL to “fast-lock”. Once locked the PLL will use the locked bandwidth setting. If the acquisition bandwidth setting is not used, the PLL will use the locked bandwidth setting at all times. Output Dividers The 8T49N241 supports one integer output divider and three fractional output dividers. Each integer output divider block (Q0 only) consists of two divider stages in a series to achieve the desired total output divider ratio. The first stage divider may be set to divide by 4, 5 or 6. The second stage of the divider may be bypassed (i.e. divide-by-1) or programmed to any even divider ratio from 2 to 131,070. The total divide ratios, settings and possible output frequencies are shown in Table 3. An output synchronization via the PLL_SYN bit is necessary after programming the output dividers to ensure that the outputs are synchronized. Table 3. Output Divide Ratios Fractional Output Divider Programming (Q1, Q2, Q3) For the FracN output dividers Q[1:3], the output divide ratio is given by: • Output Divide Ratio = (N.F)x2 • N = Integer Part: 4, 5, ...(218-1) • F = Fractional Part: [0, 1, 2, ...(228-1)]/(228) For integer operation of these output dividers, N = 3 is also supported for the full output frequency range. The minimum output divide ratio defined above is valid for all CLK_SEL modes. 1st-Stage Divide 2nd-Stage Divide Total Divide Minimum FOUT MHz Maximum FOUT MHz 4 1 4 750 1000 5 1 5 600 800 6 1 6 500 666.7 4 2 8 375 500 5 2 10 300 400 6 2 12 250 333.3 4 4 16 187.5 250 5 4 20 150 200 6 4 24 125 166.7 ... 4 131,070 524,280 0.0057 0.0076 5 131,070 655,350 0.0046 0.0061 6 131,070 786,420 0.0038 0.0051 |
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