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MAX5150BCPE Datasheet(PDF) 3 Page - Maxim Integrated Products

Part # MAX5150BCPE
Description  Low-Power, Dual, 13-Bit Voltage-Output DACs with Serial Interface
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5150BCPE Datasheet(HTML) 3 Page - Maxim Integrated Products

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Low-Power, Dual, 13-Bit Voltage-Output DACs
with Serial Interface
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS—MAX5150 (continued)
(VDD = +5V ±10%, VREFA = VREFB = 2.048V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at TA= +25°C (OS_ tied to AGND for a gain of +2).)
CONDITIONS
Rail-to-rail (Note 2)
To 1/2LSB of full-scale, VSTEP = 4V
ISOURCE = 2mA
UNITS
ISINK = 2mA
k
24
34
ROS
OSA or OSB Input Resistance
V
0 to VDD
Output Voltage Swing
µs
16
Output Settling Time
V/µs
0.75
SR
Voltage Output Slew Rate
VOL
Output Low Voltage
V
0.13
0.4
MIN
TYP
MAX
SYMBOL
PARAMETER
VOH
Output High Voltage
V
VDD - 0.5
µs
25
Time Required to Exit Shutdown
CS = VDD, fDIN = 100kHz, VSCLK = 5Vp-p
nV-s
5
Digital Feedthrough
nV-s
5
Digital Crosstalk
V
4.5
5.5
VDD
Positive Supply Voltage
(Note 3)
mA
0.5
0.65
IDD
Power-Supply Current
(Note 3)
µA
2
10
IDD (SHDN)
Power-Supply Current
in Shutdown
µA
0
±1
Reference Current in Shutdown
ns
100
tCP
SCLK Clock Period
ns
40
tCH
SCLK Pulse Width High
ns
40
tCL
SCLK Pulse Width Low
ns
40
tCSS
CS Fall to SCLK Rise
Setup Time
ns
0
tCSH
SCLK Rise to CS Rise Hold Time
ns
40
tDS
SDI Setup Time
ns
0
tDH
SDI Hold Time
CLOAD = 200pF
ns
80
tDO1
SCLK Rise to DOUT
Valid Propagation Delay
Note 1: Accuracy is specified from code 12 to code 8191.
Note 2: Accuracy is better than 1LSB for VOUT_ greater than 6mV and less than VDD - 50mV. Guaranteed by PSRR test at the end
points.
Note 3: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = ∞.
CLOAD = 200pF
ns
80
tDO2
SCLK Fall to DOUT
Valid Propagation Delay
ns
40
tCS1
CS Rise to SCLK Rise Hold
ns
100
tCSW
CS Pulse Width High
ns
10
tCS0
SCLK Rise to CS Fall Delay
DYNAMIC PERFORMANCE
POWER SUPPLIES
DIGITAL OUTPUTS
TIMING CHARACTERISTICS


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