MAX5152 datasheet(3/20 Pages) MAXIM

Part #	MAX5152

Description	Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs

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Manufacturer	MAXIM [Maxim Integrated Products]

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Low-Power, Dual, 13-Bit Voltage-Output DACs

with Configurable Outputs

_______________________________________________________________________________________

3

ELECTRICAL CHARACTERISTICS—MAX5152 (continued)

(VDD = +5V ±10%, VREFA = VREFB = 2.5V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at

TA = +25°C, output buffer connected in unity-gain configuration (Figure 9).)

Note 1: Accuracy is specified from code 20 to code 8191.

Note 2: Accuracy is better than 1LSB for VOUT greater than 6mV and less than VDD - 50mV. Guaranteed by PSRR test at the end

points.

Note 3: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = ∞.

Note 4: SCLK minimum clock period includes rise and fall times.

CS = VDD, fDIN = 100kHz, VSCLK = 5Vp-p

ISOURCE = 2mA

Rail-to-rail (Note 2)

To 1/2LSB of full-scale, VSTEP = 2.5V

ISINK = 2mA

CONDITIONS

nV-s

5

Digital Crosstalk

nV-s

5

Digital Feedthrough

µs

25

Time Required to Exit

Shutdown

µA

0

±0.1

IFB_

Current into FBA or FBB

V

VDD -

0.5

VOH

Output High Voltage

V

0 to VDD

Output Voltage Swing

µs

20

Output Settling Time

V

0.13

0.40

VOL

Output Low Voltage

V/µs

0.75

SR

Voltage Output Slew Rate

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

(Note 4)

(Note 3)

ns

40

tCL

SCLK Pulse Width Low

ns

40

tCH

SCLK Pulse Width High

ns

100

tCP

SCLK Clock Period

µA

±1

Reference Current in

Shutdown

µA

2

10

IDD(SHDN)

Power-Supply Current in

Shutdown

mA

0.5

0.65

IDD

Power-Supply Current

V

4.5

5.5

VDD

Positive Supply Voltage

ns

40

tDS

DIN Setup Time

ns

0

tCHS

SCLK Rise to CS Rise Hold

Time

ns

40

tCSS

CS Fall to SCLK Rise Setup

Time

CLOAD = 200pF

ns

80

tDO2

SCLK Fall to DOUT Valid

Propagation Delay

ns

80

tDO1

SCLK Rise to DOUT Valid

Propagation Delay

ns

0

tDH

DIN Hold Time

ns

100

tCSW

CS Pulse Width High

ns

40

tCS1

CS Rise to SCLK Rise Hold

ns

10

tCS0

SCLK Rise to CS Fall Delay

DIGITAL OUTPUTS (DOUT, UPO)

DYNAMIC PERFORMANCE

POWER SUPPLIES

TIMING CHARACTERISTICS

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