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MAX500BEWE Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX500BEWE Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 12 page sink, as well as source up to 5mA. This is especially important in single-supply applications, where VSS is connected to AGND, so that the zero error is kept at or under 1/2LSB (VREF = +10V). A plot of the Output Sink Current vs. Output Voltage is shown in the Typical Operating Characteristics section. Digital Inputs and Interface Logic The digital inputs are compatible with both TTL and 5V CMOS logic; however, the power-supply current (IDD) is somewhat dependent on the input logic level. Supply current is specified for TTL input levels (worst case) but is reduced (by about 150µA) when the logic inputs are driven near DGND or 4V above DGND. Do not drive the digital inputs directly from CMOS logic running from a power supply exceeding 5V. When driv- ing SCL through an opto-isolator, use a Schmitt trigger to ensure fast SCL rise and fall times. The MAX500 allows the user to choose between a 3-wire serial interface and a 2-wire serial interface. The choice between the 2-wire and the 3-wire inter- face is set by the LOAD signal. If the LOAD is allowed to float (it has a weak internal pull-up resistor to VDD), the 2-wire interface is selected. If the LOAD signal is kept to a TTL-logic high level, the 3-wire interface is selected. 3-Wire Interface The 3-wire interface uses the classic Serial Data (SDA), Serial Clock (SCL), and LOAD signals that are used in standard shift registers. The data is clocked in on the falling edge of SCL until all 10 bits (8 data bits and 2 address bits) are entered into the shift register. CMOS, Quad, Serial-Interface 8-Bit DAC 6 _______________________________________________________________________________________ INPUT (5V/div) OUTPUT (20mV/div) DYNAMIC RESPONSE (VSS = -5V or 0V) 2 µs/div LDAC 5V/div OUTPUT 5V/div VSS VDD PMOS (+) FROM INVERTED DAC OUTPUT INPUTS CC (-) NPN EMITTER FOLLOWER PULL-UP VOUT NMOS ACTIVE PULL-DOWN CIRCUIT Figure 2. Positive and Negative Settling Times Figure 3. Dynamic Response Figure 4. Simplified Output Buffer Circuit POSITIVE STEP (VSS = -5V or 0V) 1 µs/div LDAC 5V/div OUTPUT 100mV/div NEGATIVE STEP (VSS = -5V or 0V) 1 µs/div LDAC 5V/div OUTPUT 100mV/div |
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