The MAX473/MAX474/MAX475 have excellent phase

margin (the difference between 180° and the unity-gain

phase angle). It is typically 63° with a load of 10k

Ω in

parallel with 20pF. Generally, higher phase margins

indicate greater stability.

Capacitive loads form an RC network with the op amp’s

output resistance, causing additional phase shift that

reduces the phase margin. Figure 3 shows the

MAX473/MAX474/MAX475 output response when dri-

ving a 390pF load in parallel with 10k

Ω.

When driving large capacitive loads, add an output iso-

lation resistor, as shown in Figure 4. This resistor

improves the phase margin by isolating the load

capacitance from the amplifier output. Figure 5 shows

the MAX473/MAX474/MAX475 driving a capacitive load

of 1000pF using the circuit of Figure 4.

Feedback Resistors

The feedback resistors appear as a resistance network

to the op amp’s feedback input (Figure 2). This resis-

tance, combined with the op amp’s input and stray

capacitance (total input capacitance), forms a pole that

adds unwanted phase shift when either the total input

capacitance or feedback resistance is too large. For

example, using the noninverting configuration with a

gain of 10, if the total capacitance at the negative input

is 10pF and the effective resistance (R1

tional phase shift, which reduces the overall bandwidth

and adversely affects stability. Choose feedback resis-

tors small enough so they do not adversely affect the

op amp’s operation at the frequencies of interest.

Overdriving the Outputs

The output voltage swing for specified operation is from

Exercising the outputs beyond these limits drives the out-

put transistors toward saturation, resulting in bandwidth

degradation, response-time increase, and gain decrease

(which affects linearity). Operation in this region causes a

slight distortion in the output waveform, but does not

adversely affect the op amp.

Single/Dual/Quad, 10MHz

Single-Supply Op Amps

10

______________________________________________________________________________________

MAX473

NULL

2k

NULL

1

4

8

R1

R2

R3

R3 = R2

R1

R3

R2

R1

R3 = R2

R1

Figure 1. Offset Null Circuit

Figure 2a. Reducing Offset Error Due to Bias Current:

Inverting Configuration

Figure 2b. Reducing Offset Error Due to Bias Current:

Noninverting Configuration