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TPS7B7702-Q1 Datasheet(PDF) 7 Page - Texas Instruments |
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TPS7B7702-Q1 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 23 page TPS7B7701-Q1, TPS7B7702-Q1 www.ti.com SLVSCE8A – JANUARY 2015 – REVISED MAY 2015 Electrical Characteristics (continued) VI = 14 V, TJ = –40ºC to +150ºC, unless otherwise stated PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IO = 100 to 300 mA –3% 3% IO = 50 to 100 mA –5% 5% OUTx to SENSEx current ratio accuracy IO = 10 to 50 mA –10% 10% IO = 5 to 10 mA –20% 20% IO/ILIM OUTx to LIMx current ratio (IO / ILIM) VI = 4.5 V to 40 V, 50 mA ≤ I(LIMx) ≤ 300 mA 198 I(LIMx) Programmable current-limit accuracy(3) VI = 4.5 V to 40 V, 50 mA ≤ I(LIMx) ≤ 300 mA –8% 8% IL(LIMx) Internal current-limit LIMx shorted to GND 340 550 mA SENSE, SENSE1, SENSE2, LIM, LIM1, Ilkg ENx = GND, TA = 25°C 2 µA and LIM2 leakage current Voltage on the LIM, LIM1, and LIM2 pins when V(LIMx_th) Current-limit threshold voltage –4% 1.233 4% V output current is limited When short-to-battery or reverse current V(SENSEx_stb) Current-sense short-to-battery fault voltage 3.05 3.2 3.3 V conditions are detected Current-sense thermal shutdown fault V(SENSEx_tsd) When thermal shutdown is detected 2.7 2.85 3 V voltage V(SENSEx_cl) Current-sense current-limit fault voltage When current-limit conditions are detected 2.4 2.55 2.65 V When short-to-battery, reverse current, thermal I(SENSEx_H) Current-sense fault condition current shutdown, or current-limit conditions are 3.3 mA detected FAULT DETECTION V(stb_th) Short-to-battery threshold V(OUTx) – VI, checked during turnon sequence –500 –55 110 mV I(REV) Reverse current detection level Power FET on (SW or LDO mode) –100 –40 –1 mA TSD Thermal shutdown Junction temperature 175 °C TSD(hys) Thermal shutdown hysteresis 15 °C INTERFACE CIRCUITRY VOL ERR output low I(SINK) = 5 mA 0.4 V ERR high impedance, 5-V external voltage is Ilkg ERR open-drain leakage current 1 µA applied at ERR R(OUTx-off) OUT pulldown resistor(2) ENx = GND 50 k Ω IR(lkg) Reverse leakage current –40 V < VI < 0 V, reverse current to IN 0.6 mA VCC Internal voltage regulator VI = 5.5 to 40 V, ICC = 0 mA 4.25 4.5 4.75 V ICC(lim) Internal voltage-regulator current-limit 15 70 mA (3) The current-limit accuracy is ensured when the LIMx pin is between 50 mA and 300 mA. 6.6 Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT SENSE AND CURRENT-LIMIT Current-sense delay time from the rising edge V(ENx) ≥ 2 V, SENSE_EN = GND, td(SENSE_SEL_r) 10 µs of SENSE_SEL(1) SENSE_SEL rise from 0 to 5 V Current-sense delay time from the falling edge V(ENx) ≥ 2 V, SENSE_EN = GND, td(SENSE_SEL_f) 10 µs of SENSE_SEL(1) SENSE_SEL fall from 5 to 0 V Current-sense delay time from rising edge of V(ENx) ≥ 2 V, SENSE_EN rise from 0 to td(SENSE_EN_r) 10 µs SENSE_EN(1) 5 V Current-sense delay time from falling edge of V(ENx) ≥ 2 V, SENSE_EN fall from 5 to td(SENSE_EN_f) 10 µs SENSE_EN(1) 0 V FAULT DETECTION Delay to shut down the switch or LDO Reverse current (Short-to-BAT) shutdown t(PD_RC) after a drop over ron becomes negative, 5 20 µs deglitch time I(OUTx) = –200 mA (typical), TA = 25°C Blanking time for reverse-current detection after power up, the rising t(BLK_RC) Reverse current blanking time 16 ms edge of the ENx pin, or the current limiting event is over (1) Design information — not tested, ensured by characterization. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS7B7701-Q1 TPS7B7702-Q1 |
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