BQ24031-Q1 datasheet(6/35 Pages) TI

Part #	BQ24031-Q1

Description	SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC

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Manufacturer	TI [Texas Instruments]

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bq24030-Q1

bq24031-Q1

SLUS793B – APRIL 2008 – REVISED OCTOBER 2009.................................................................................................................................................... www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

over junction temperature range (0°C

≤ TJ ≤ 125°C) and recommended supply voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Charge Termination Detection

Charge termination

I(TERM)

VI(BAT) < V(RCH), I(TERM) = (K(SET) × V(TERM))/RSET

10

150

mA

detection range

AC-charge termination

V(TERM-AC)

detection voltage,

VI(BAT) > V(RCH) , PSEL = high, ACPG = low

235

250

265

mV

measured on ISET1

USB-charge termination

VI(BAT) > V(RCH),

V(TAPER-USB)

detection voltage,

95

100

130

mV

PSEL = low or PSEL = high and ACPG = high

measured on ISET1

Deglitch time for

tFALL = 100 ns, 10-mV overdrive,

TDGL(TERM)

22.5

ms

termination detection

ICHG increasing above or decreasing below threshold

Temperature Sense Comparators

VLTF

High voltage threshold

Temperature fault at V(TS) > VLTF

2.465

2.500

2.535

V

VHTF

Low voltage threshold

Temperature fault at V(TS) < VHTF

0.485

0.500

0.515

V

Temperature sense current

ITS

94

100

106

μA

source

Deglitch time for

R(TMR) = 50 kΩ, VI(BAT) increasing or decreasing above

TDGL(TF)

temperature fault

22.5

ms

and below; 100-ns fall time, 10-mV overdrive

detection(14)

Battery Recharge Threshold

Recharge threshold

VO(BAT-REG)

VRCH

V

voltage

– 0.075

– 0.100

– 0.125

Deglitch time for recharge

R(TMR) = 50 kΩ, VI(BAT) increasing or decreasing below

TDGL(RCH)

22.5

ms

detection(14)

threshold, 100-ns fall time, 10-mV overdrive

STAT1, STAT2. ACPG, USBPG Open-Drain (OD) Outputs(15)

Low-level output saturation

VOL

IOL = 5 mA, External pullup resistor ≥ 1 kΩ required

0.25

V

voltage

ILKG

Input leakage current

1

5

μA

ISET2, CE Inputs

VIL

Low-level input voltage

0

0.4

V

VIH

High-level input voltage

1.4

IIL

Low-level input current, CE

–1

μA

High-level input current,

IIH

1

μA

CE

Low-level input current,

IIL

VISET2 = 0 V

–20

μA

ISET2

High-level input current,

IIH

VISET2 = VCC

40

μA

ISET2

IIL1

Low-level input current

6

1

μA

IIH1

High-level input current

15

μA

t(CE-HLDOFF)

Holdoff time, CE

CE going low only

3.3

6.2

ms

PSEL Input

VIL

Low-level input voltage

Falling high

→low, 280 kΩ ± 10% applied when low

0.975

1

1.025

V

VIH

High-level input voltage

Input RPSEL sets external hysteresis

VIL + 0.01

VIL + 0.024

V

Low-level input current,

IIL

–1

μA

PSEL

High-level input current,

IIH

μA

PSEL

(14) All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the

program current is reduced.

(15) See Charger Sleep mode for ACPG (VCC = VAC) and USBPG (VCC = VUSB) specifications.

6

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