±15kV ESD-Protected, Low-Voltage, CMOS

Analog Multiplexers/Switches

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11

Test Circuits/Timing Diagrams

50%

0V

0V

90%

90%

50%

0V

0V

90%

90%

50%

0V

0V

90%

90%

GND

B

A

C

ENABLE

X0

X1–X7

X

MAX4558

300

Ω

50

Ω

35pF

GND

B

A

ENABLE

X0, Y0

X1–X3, Y1–Y3

X, Y

MAX4559

300

Ω

50

Ω

35pF

GND

ENABLE

X1, Y1, Z1

X0, Y0, Z0

X, Y, Z

MAX4560

300

Ω

35pF

B

A

C

50

Ω

V- = 0 FOR SINGLE-SUPPLY OPERATION.

REPEAT TEST FOR EACH SECTION.

Figure 1. Switching Times