Serially Controlled, Clickless

Audio/Video Switches

10

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Detailed Description

The MAX4571–MAX4574 are serial-interface controlled

switches with soft-mode “clickless” and hard-mode oper-

ating capability. The MAX4571/MAX4573 contain 11

SPST switches, while the MAX4572/MAX4574 contain

two SPST switches and six SPDT switches. The SPDT

switches are actually 2-to-1 multiplexers, in that each

SPDT is really two independent SPST switches with a

common node, as shown in the

Pin Configurations. Each

switch is controlled independently by either the SPI or

Audio off-isolation is -90dB at 20kHz, crosstalk is at

least -90dB at 20kHz, and video off-isolation is at least

-50dB at 10MHz.

Each switch of any device may be set to operate in

either soft or hard mode. In soft mode, the switching

transition is slowed to avoid the audible “clicking” that

can occur when switches are used to route audio sig-

nals. In hard mode, the switches are not slowed down,

making this mode useful when a faster response is

required. If a new command is issued while any soft-

mode switch is transitioning, the switch transition time

is decreased so it reaches its final state before the new

command is executed. Soft mode is the power-up

default state for all switches. Switches in the same

mode are guaranteed to be break-before-make relative

to each other. Break-before-make does not apply

between switches operating in different modes.

These devices operate from a single supply of +2.7V to

compatible serial interface, and the MAX4573/

MAX4574 feature a 3-wire, SPI/QSPI/MICROWIRE-com-

patible serial interface.

Applications Information

Switch Control

The MAX4571–MAX4574 have a common command

and control-bit structure, the differences being only in

the interface type (2-wire or 3-wire) and in the switch

configurations.

The SWITCHSET command controls the open/closed

states of the various switches. MODESET controls

soft/hard-mode states of the switches. There are also

NO_OP and RESET commands. The NO_OP command

is useful for daisy-chaining multiple 3-wire parts. The

RESET command places a device in a state identical to

its power-up state, with all switches open and in soft

switching mode.

Table 1 shows the configuration of the command bits

and their related commands. Table 2 shows the config-

uration of the data bits and their related switches. The

arrangement of the command bits and the data bits

depends on the interface type (2-wire or 3-wire). After a

SWITCHSET command is issued, a logic 1 in any data-

bit location closes the associated switch, while a logic 0

opens it. After a MODESET command, a logic 1 in any

data-bit location sets the associated switch into hard

mode, while a logic 0 sets it into soft mode.

2-Wire Serial Interface

serial interface requiring only two I/O lines of a stan-

dard microprocessor port for communication. These

devices use the SendByte™ and WriteWord™ proto-

cols. The SendByte protocol is used only for the RESET

command. The WriteWord protocol is used for the

MODESET and SWITCHSET commands.

The first byte of any 2-wire serial-interface transaction is

always the address byte. To address a given chip, the

A0 and A1 bits in the address byte (Table 3) must dupli-

cate the values present at the A0 and A1 pins of that

chip, and the rest of the address bits must be config-

ured as shown in Table 3. Connect the A0 and A1 pins

to V+ or to GND, or drive them with CMOS logic levels.

The second byte is the command byte. The possible

commands are RESET, MODESET, and SWITCHSET.

RESET sets all switches to the initial power-up state

(open and in soft switching mode). The RESET com-

mand is executed on the rising clock edge of the

acknowledge bit after the command byte. The MODE-

SET and SWITCHSET commands are each followed by

two data bytes. The first data byte is buffered so all the

data latches switch together. MODESET and SWITCH-

SET are executed on the rising clock edge of the

acknowledge bit after the second data byte. Table 3

details the 2-wire interface data structure. Figures 3

and 4 and the

I/O Interface Characteristics detail the

timing of the 2-wire serial-interface protocol. All bytes of

the transmission, whether address, command, or data,

are sent MSB first.

The MAX4571/MAX4572 are receive-only devices and

must be controlled by a bus master device. A bus mas-

ter signals the beginning of a transmission with a start

condition by transitioning SDA from high to low while

SCL is high. The slave devices monitor the serial bus

continuously, waiting for a start condition followed by an

address byte. When a device recognizes its address

byte, it acknowledges by pulling the SDA line low for

one clock period; it is then ready to accept command

and data bytes. The device then issues a similar

acknowledgment after the command byte, and again

after each data byte. When the master has finished

SendByte and WriteWord are trademarks of Philips Corp.