8x4 Video Crosspoint Switches with Buffers

10

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to their switch registers. As long as either

–

W

—

R

–

or

–

C

—

E

–

is

high, the input register will not change. The switch reg-

ister will pass any new data on the falling transition of

–

U

—

P

—

D

—

A

—

T

—

E

–

.

Each register of the switch-register bank controls the

inputs to one amplifier. With

–

U

—

P

—

D

—

A

—

T

—

E

–

low, the switch

registers are transparent and switch connection is con-

trolled by the input register. However, if

–

U

—

P

—

D

—

A

—

T

—

E

–

is

high, the switch register is latched and any change in

data by the input register will not affect the amplifier

output state. Two register banks are used so that data

can be loaded into input registers without affecting the

switch/amplifier selection. This allows amplifiers to be

programmed and then changed simultaneously. When

the registers are not latched, they are made transparent.

Use data bit D3 to disable the amplifier selected by

A0–A1 and place its output in high-impedance mode.

As an example, the code to disable OUT0 is as follows:

Pin Name: D3 D2 D1 D0 A1 A0

Input Code: 1 X

X

X

0

0

When operating in parallel mode, C

—

S

–

must be wired high

and SCLK and DIN should be grounded, as shown in

Figure 3. Refer to Figure 4 for the correct timing rela-

tionships.

Digital Section—Serial Mode

The MAX458/MAX459 use a three-wire serial interface

that is compatible with SPI, QPSI and Microwire inter-

faces. Serial mode, shown in Figure 5, is enabled

when

–

W

—

R

–

,

–

U

—

P

—

D

—

A

—

T

—

E

–

, and

–

C

—

E

–

are held high and

–

C

—

S

–

goes

low. Figures 6 and 7 show serial-mode timing. Figure 8

shows the MAX458/MAX459 configured for serial oper-

ation. Figure 9 shows the Microwire connection, and

Figure 10 shows the SPI/QSPI connection.

The serial output, DOUT, allows cascading of two or

more crosspoint switches to create larger arrays. The

data at DOUT is delayed by 16 cycles plus one clock

pulse width at DIN. DOUT changes on SCLK’s falling

edge when

–

C

—

S

–

is low. When

–

C

—

S

–

is high, DOUT remains

in the state of the last data bit.

The MAX458/MAX459 input data in 16-bit blocks. SPI

and Microwire interfaces output data in 8-bit blocks,

thereby requiring two write cycles to input data. The

QSPI interface allows variable word lengths from 8 to 16

bits and can be loaded into the crosspoint in one write

cycle. SPI and Microwire limit clock rates to 2MHz, while

the QSPI maximum clock rate is 4MHz.

ADDRESS VALID

A0/A1

CE

WR

UPDATE

DATA VALID

D0–D3

Figure 4. Parallel-Mode Timing