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MAX4559EPE Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX4559EPE Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 16 page ESD Test Conditions ESD performance depends on several conditions. Contact Maxim for a reliability report that documents test setup, methodology, and results. Human Body Model Figure 6 shows the Human Body Model, and Figure 7 shows the current waveform it generates when dis- charged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of inter- est, which is then discharged into the test device through a 1.5k Ω resistor. Power-Supply Considerations The MAX4558/MAX4559/MAX4560 are typical of most CMOS analog switches. They have three supply pins: VCC, VEE, and GND. VCC and VEE drive the internal CMOS switches and set the limits of the analog voltage on every switch. Internal reverse ESD-protection diodes connect between each analog signal pin and both VCC and VEE. If any analog signal exceeds VCC or VEE, one of these diodes conducts. The only currents drawn from VCC or VEE during normal operation are the leak- age currents of these ESD diodes. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either VCC or VEE and the analog signal. Their leakage currents vary as the signal varies. The difference in the two diode leakages to the VCC and VEE pins constitutes the analog signal-path leakage current. All analog leakage current flows between each input and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of either the same or opposite polarity. VCC and GND power the internal logic and logic-level translators, and set the input logic limits. The logic-level translators convert the logic levels into switched VCC and VEE signals to drive the gates of the analog switch. This drive signal is the only connection between the logic supplies and logic signals and the analog sup- plies. VCC and VEE have ESD-protection diodes to GND. The logic-level thresholds are TTL/CMOS compatible when VCC is +5V. As VCC rises, the threshold increases slightly. When VCC reaches +12V, the threshold is about 3.1V (above the TTL-guaranteed high-level mini- mum of 2.4V, but still compatible with CMOS outputs). High-Frequency Performance In 50 Ω systems, signal response is reasonably flat up to 50MHz (see Typical Operating Characteristics). Above 20MHz, the on response has several minor peaks that are highly layout dependent. The problem is not turning the switch on, but turning it off. The off-state switch acts like a capacitor and passes higher frequen- cies with less attenuation. At 1MHz, off-isolation is about -68dB in 50 Ω systems, becoming worse (approx- imately 20dB per decade) as the frequency increases. Higher circuit impedance also degrades off-isolation. Adjacent channel attenuation is about 3dB above that of a bare IC socket and is entirely due to capacitive coupling. ±15kV ESD-Protected, Low-Voltage, CMOS Analog Multiplexers/Switches 10 ______________________________________________________________________________________ |
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