8 x 8 Video Crosspoint Switch

10

______________________________________________________________________________________

DATA (N)

DATA (N)

DATA (N)

DATA (N + 1)

DATA (N + 1)

DATA (N + 1)

DATA (N + 2)

DATA (N)

DATA (N + 1)

DATA (N + 2)

SEE FIGURE 4 FOR WR

AND LATCH TIMING

WR

LATCH

FIRST-RANK REGISTER DATA

SECOND-RANK REGISTER DATA

(EDGE/LEVEL = Low)

SECOND-RANK REGISTER DATA

(EDGE/LEVEL = High)

_______________________________________________Timing Diagrams (continued)

Figure 5. Parallel-Interface Mode Format (SER/

–

P

—

A

—

R

–

= Low)

0D3

0D2

0D1

0D0

1D3

1D2

7D3

7D2

7D1

7D0

DATA VALID

DATA VALID

SEE TABLE 2 FOR

INPUT DATA

SEE FIGURE 4 FOR WR

AND LATCH TIMING

WR

LATCH

INPUT DATA FOR OUT0

INPUT DATA FOR OUT1 TO OUT6

INPUT DATA FOR OUT7

SECOND-RANK REGISTER DATA

(EDGE/LEVEL = Low)

SECOND-RANK REGISTER DATA

(EDGE/LEVEL = High)

Figure 6. 32-Bit Serial-Mode Interface Format (SER/

–

P

—

A

—

R

–

= High)