Quad, Rail-to-Rail, Fault-Protected,

SPDT Analog Switch

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11

Test Circuits/Timing Diagrams (continued)

50%

VO1

VO2

0.9VO

+3V

0V

VCOM

0V

VCOM

LOGIC

INPUT

SWITCH

OUTPUT

SWITCH

OUTPUT

+15V

V+

NO

V-

-15V

CL INCLUDES FIXTURE AND STRAY CAPACITANCE.

LOGIC 0 INPUT.

GND

LOGIC

INPUT

0V

0.9VO

tD

tD

RL2

NC

CL2

VO2

VO1

CL1

RL = 1000Ω

CL = 35pF

COM_

RL1

IN_

MAX4533

Figure 3. Break-Before-Make

0V

V+

TRANSFER ERROR Q WHEN THE CHANNEL TURNS OFF.

V- IS CONNECTED TO GND (0V) FOR SINGLE-SUPPLY OPERATION.

Q =

V+

GND

V+

V-

V-

IN_

NC_ OR NO_

MAX4533

50

Ω

CL

100pF

Figure 4. Charge Injection

V- IS CONNECTED TO GND (0V) FOR SINGLE-SUPPLY OPERATION.

V+

V+

GND

V+

V-

V-

IN_

NO_

COM_

MAX4533

NC_

ADDRESS SELECT

1MHz

CAPACITANCE

ANALYZER

Figure 5. COM_, NO_, NC_ Capacitance