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85356 Datasheet(PDF) 9 Page - Integrated Device Technology

Part # 85356
Description  Propagation delay
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

85356 Datasheet(HTML) 9 Page - Integrated Device Technology

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2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL/ECL CLOCK
MULTIPLEXER
9
Rev C 1/5/15
85356 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 85356.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 85356 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VCC_MAX * IEE_MAX = 3.6V * 40mA = 144mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.6V, with all outputs switching) = 144mW + 60mW = 204mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 83.2°C/W per Table 6B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.204W * 73.2°C/W = 99.9°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (single layer or multi-layer).
Table 6A. Thermal Resistance JA for 20 Lead SOIC, Forced Convection
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Table 6B. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
JA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
JA by Velocity
Linear Feet per Minute
0200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W


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