LOW SKEW 1 TO 2 CLOCK BUFFER

2

REVISION A 03/18/15

74FCT38072S DATASHEET

Pin Assignments

Pin Descriptions

External Components

A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF should be

connected between VDD pin and GND pin, as close to the device as possible. A 33

 series terminating resistor may be used

on each clock output if the trace is longer than 1 inch.

To achieve the low output skew that the 74FCT38072S is capable of, careful attention must be paid to board layout. Essentially,

both outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will

be degraded. For example, using a 30

 series termination on one output (with 33 on the others) will cause at least 15 ps of

skew.

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

VDD

Power

Connect to +1.8V, +2.5 V, or +3.3 V.

2

VDD

Power

Connect to +1.8V, +2.5 V, or +3.3 V.

3

ICLK

Input

Clock input.

4

GND

Power

Connect to ground.

5

GND

Power

Connect to ground.

6

Q0

Output

Clock output 0.

7

Q1

Output

Clock output 1.

8

GND

Power

Connect to ground.

1

2

3

VDD

4

Q0

Q1

GND

ICLK

8

7

6

5

8-pin SOIC

VDD

GND

GND

1

2

3

VDD

4

Q0

Q1

GND

ICLK

8

7

6

5

8-pin DFN

GND

GND

VDD