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STC5423 Datasheet(PDF) 7 Page - Connor-Winfield Corporation |
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STC5423 Datasheet(HTML) 7 Page - Connor-Winfield Corporation |
7 / 60 page Page 7 of 60 TM114 Rev:1.4 Date: October 24, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5423 Synchronous Clock for SETS Data sheet CLK6 93 O Clock output CLK6. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G6 or Synthe- sizer GT4 (T4). LVCMOS. CLK7 94 O Clock output CLK7. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G7 or Synthe- sizer GT4 (T4). LVCMOS. CLK8K 30 O 8kHz frame pulse signal, 50% duty cycle or programmable pulse width (T0) CLK2K 31 O 2kHz frame pulse signal, 50% duty cycle or programmable pulse width (T0) SRCSW 18 I Hard-wired manual reference input pre-selection MPU_MODE0 60 I Bus interface: Intel, Motorola, Multiplexed, SPI MPU_MODE1 59 I MPU_MODE2 58 I CS 70 I SPI bus chip select WR 71 I Write access for Intel, Motorola and Multiplex bus interface RD 72 I Read access for Intel and Multiplex bus interface ALE/SCLK 73 I ALE: Address latch enable for Multiplex bus interface SCLK: Clock edge selection for SPI RDY 75 O Ready/Data Acknowledge for Intel, Motorola and Multiplex bus interface A0/SDI 69 I A0~A6: Address pins for bus interface Intel and Motorola SDI: SPI bus data input CLKE: Clock edge selection for SPI A1/CLKE 68 I A2 67 I A3 66 I A4 65 I A5 64 I A6 63 I AD0/SDO 83 I/O AD0~AD7: Bus interface Intel and Motorola data pins Multiplex data and address pins SDO: SPI bus data output AD1 82 I/O AD2 81 I/O AD3 80 I/O AD4 79 I/O AD5 78 I/O AD6 77 I/O AD7 76 I/O Table 1: Pin Description Pin Name Pin # I/O Description |
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