Serially Controlled, Low-Voltage,

8-Channel SPST Switch

6

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TIMING CHARACTERISTICS—Single +5V Supply (Figure 1)

Note 1: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.

Note 2:

specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as

measured over the specified analog signal range.

Note 3: Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp.

Note 4: Guaranteed by design.

Note 5: Leakage testing at single supply is guaranteed by testing with dual supplies.

Note 7: Between any two switches. See Figure 3.

SERIAL DIGITAL INTERFACE

SERIAL DIGITAL INTERFACE

Rise Time of DOUT (Note 4)

100

ns

20% of V+ to 70% of V+,

C, E, M

Allowable Fall Time at DIN,

SCLK (Note 4)

2

µs

20% of V+ to 70% of V+,

C, E, M

Allowable Rise Time at DIN,

SCLK (Note 4)

2

µs

20% of V+ to 70% of V+,

C, E, M

DIN Data Valid after Falling SCLK

(Note 4)

400

ns

Data Hold Time (Note 4)

Data Setup Time (Note 4)

200

17

ns

0

-17

85

50% of SCLK to 10% of

SCLK Low Time (Note 4)

ns

C, E, M

190

ns

C, E, M

C, E, M

PARAMETER

SYMBOL

MIN

TYP

MAX

(Note 2)

UNITS

C, E, M

SCLK High Time (Note 4)

CS Lag Time (Note 4)

240

ns

190

CS Lead Time (Note 4)

Cycle Time (Note 4)

SCLK Frequency

ns

0

2.1

MHz

480

240

ns

C, E, M

ns

C, E, M

C, E, M

C, E, M

C, E, M

CONDITIONS

C, E, M

20% of V+ to 70% of V+,

ns

100

Fall Time of DOUT (Note 4)

RESET Minimum Pulse Width

70

ns