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8SLVP2104 Datasheet(PDF) 5 Page - Integrated Device Technology |
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8SLVP2104 Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 23 page REVISION C 6/8/15 5 LOW PHASE NOISE, DUAL 1-TO-4, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER 8SLVP2104 DATA SHEET AC Electrical Characteristics Table 4A. AC Electrical Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crosspoint. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew within a bank with equal load conditions. Measured at the differential crosspoints. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints. NOTE 6: VIL should not be less than -0.3V. VIH should not be higher than VCC. NOTE 7: Common mode input voltage is defined as the crosspoint. NOTE 8: For single-ended LVCMOS input applications, please refer to the Applications Information, Wiring the Differential Input to accept single-ended levels, Figures 1A and 1B. Symbol Parameter Test Conditions Minimum Typical Maximum Units fREF Input Frequency PCLKA, nPCLKA; PCLKB, nPCLKB 2GHz V/t Input Edge Rate PCLKA, nPCLKA; PCLKB, nPCLKB 1.5 V/ns tPD Propagation Delay; NOTE 1 PCLKA, nPCLKA to any QAx, nQAx or PCLKB, nPCLKB to any QBx, nQBx for VPP = 0.1V or 0.3V 50 165 270 ps Channel_ISOL Channel Isolation fREF = 122.88MHz 78 dB tsk(o) Output Skew; NOTE 2, 3 Any Output 8 25 ps tsk(b) Bank Skew; NOTE 3, 4 Within QAx, QBx 7 20 ps tsk(p) Pulse Skew fREF = 100MHz 7 27 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 100 200 ps tJIT, SP Spurious Suppression, Coupling from QA3 to QB0 fQB0 = 500MHz, VPP(PCLKB) = 0.15V, VCMR(PCLKB) = 1V and fQA3 = 62.5MHz, VPP(PCLKA) = 1V, VCMR(PCLKA) = 1V -66 dB fQB0 = 500MHz, VPP(PCLKB) = 0.15V, VCMR(PCLKB) = 1V and fQA3 = 15.625MHz, VPP(PCLKA) = 1V, VCMR(PCLKA) = 1V -77 dB tR / tF Output Rise/ Fall Time 20% to 80% 40 100 150 ps VPP Peak-to-Peak Input Voltage; NOTE 6, 8 fREF < 1.5 GHz 0.1 1.5 V fREF > 1.5 GHz 0.2 1.5 V VCMR Common Mode Input Voltage; NOTE 6, 7, 8 1.0 VCC – 0.6 V VO(pp) Output Voltage Swing, Peak-to-Peak VCC = 3.3V, fREF 2GHz 0.4 0.6 1.0 V VCC = 2.5V, fREF 2GHz 0.35 0.55 1.0 V VDIFF_OUT Differential Output Voltage Swing, (Peak-to-Peak) VCC = 3.3V, fREF 2GHz 0.8 1.2 2.0 V VCC = 2.5V, fREF 2GHz 0.7 1.1 2.0 V |
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