8P73S674 DATA SHEET

1.8V LVPECL CLOCK DIVIDER

8

REVISION 1 12/17/14

1.8V Differential Clock Input Interface

The IN /nIN accepts LVDS and other differential signals. The

requirements. Figure 2A to Figure 2C show interface examples for

the IN /nIN input driven by the most common driver types. The input

interfaces suggested here are examples only. If the driver is from

another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements.

Receiv er

IN

nIN

VT

LVDS

Zo = 50

Zo = 50

1.8V

3.3V, 2.5V, 1.8V

Figure 2A. Differential Input Driven by an LVDS Driver

Receiv er

IN

nIN

VT

CML

Zo = 50

Zo = 50

1.8V

1.8V

Figure 2B. Differential Input Driven by a CML Driver

Receiv er

IN

nIN

VT

LVPECL

Zo = 50

Zo = 50

1.8V

2.5V, 1.8V

Figure 2C. Differential Input Driven by an LVPECL Driver