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9DBV0831 Datasheet(PDF) 5 Page - Integrated Circuit Systems |
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9DBV0831 Datasheet(HTML) 5 Page - Integrated Circuit Systems |
5 / 19 page REVISION G 03/02/15 5 8 O/P 1.8V PCIE GEN1-2-3 ZERO-DELAY/FAN-OUT BUFFER (ZDB/FOB) 9DBV0831 DATASHEET Pin Descriptions (cont.) PIN # PIN NAME TYPE DESCRIPTION 39 VDDIO PWR Power supply for differential outputs 40 GND GND Ground pin. 41 DIF6 OUT Differential true clock output 42 DIF6# OUT Differential Complementary clock output 43 vOE6# IN Active low input for enabling DIF pair 6. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 44 DIF7 OUT Differential true clock output 45 DIF7# OUT Differential Complementary clock output 46 vOE7# IN Active low input for enabling DIF pair 7. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 47 VDDIO PWR Power supply for differential outputs 48 ^CKPWRGD_PD# IN Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. 49 EPAD GND Connect to Ground |
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