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9DBV0541 Datasheet(PDF) 8 Page - Integrated Circuit Systems

Part # 9DBV0541
Description  HCSL compatible differential input
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

9DBV0541 Datasheet(HTML) 8 Page - Integrated Circuit Systems

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5 O/P 1.8V PCIE GEN1-2-3 FAN-OUT BUFFER W/ZO=100OHMS
8
REVISION B 08/28/14
9DBV0541 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
Electrical Characteristics–Phase Jitter Parameters
TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Duty Cycle Distortion
tDCD
Measured differentially, @100MHz
-1
-0.1
1
%
1,3
Skew, Input to Output
tpdBYP
Bypass Mode, VT = 50%
1800
2342
3000
ps
1
Skew, Output to Output
tsk3
VT = 50%
37
50
ps
1,4
Jitter, Cycle to cycle
tjcyc-cyc
Additive
Jitter in Bypass Mode
0.1
5
ps
1,2
1 Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4 All outputs at default slew rate
TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
INDUSTRY
LIMIT
UNITS
Notes
tjphPCIeG1
PCIe Gen 1
0.1
5
N/A
ps (p-p) 1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1
0.4
N/A
ps
(rms)
1,2,3,4,5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.01
0.4
N/A
ps
(rms)
1,2,3,4
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.00
0.1
N/A
ps
(rms)
1,2,3,4
tjphSGMIIM0
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
165
200
N/A
fs
(rms)
1,6
tjphSGMIIM1
125MHz, 12kHz to 20MHz, -20dB/decade rollover
< 1.5MHz, -40db/decade rolloff > 10MHz
251
300
N/A
fs
(rms)
1,6
1Guaranteed by design and characterization, not 100% tested in production.
4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
5 Driven by 9FGV0831 or equivalent
6 Driven by Rohde&Schwarz SMA100
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
Additive Phase Jitter,
Bypass Mode
tjphPCIeG2
2 See http://www.pcisig.com for complete specs


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