REVISION D 04/22/15

3

5 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER

9DBU0531 DATASHEET

Pin Descriptions

Pin# Pin Name

Type

Pin Description

1vOE4#

IN

Active low input for enabling DIF pair 4. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

2

DIF4

OUT

Differential true clock output

3

DIF4#

OUT

Differential Complementary clock output

4

VDDR1.5

PWR

1.5V power for differential input clock (receiver). This VDD should be treated

as an Analog power rail and filtered appropriately.

5

CLK_IN

IN

True Input for differential reference clock.

6

CLK_IN#

IN

Complementary Input for differential reference clock.

7

GNDR

GND

Analog Ground pin for the differential input (receiver)

8

GNDDIG

GND

Ground pin for digital circuitry

9

VDDDIG1.5

PWR

1.5V digital power (dirty power)

10

SCLK_3.3

IN

Clock pin of SMBus circuitry, 3.3V tolerant.

11

SDATA_3.3

I/O

Data pin for SMBus circuitry, 3.3V tolerant.

12

vOE0#

IN

Active low input for enabling DIF pair 0. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

13

DIF0

OUT

Differential true clock output

14

DIF0#

OUT

Differential Complementary clock output

15

GND

GND

Ground pin.

16

VDDO1.5

PWR

Power supply for outputs, nominally 1.5V.

17

vOE1#

IN

Active low input for enabling DIF pair 1. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

18

DIF1

OUT

Differential true clock output

19

DIF1#

OUT

Differential Complementary clock output

20

GNDA

GND

Ground pin for the PLL core.

21

VDDA1.5

PWR

1.5V power for the PLL core.

22

DIF2

OUT

Differential true clock output

23

DIF2#

OUT

Differential Complementary clock output

24

vOE2#

IN

Active low input for enabling DIF pair 2. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

25

VDDO1.5

PWR

Power supply for outputs, nominally 1.5V.

26

GND

GND

Ground pin.

27

DIF3

OUT

Differential true clock output

28

DIF3#

OUT

Differential Complementary clock output

29

vOE3#

IN

Active low input for enabling DIF pair 3. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

30

GND

GND

Ground pin.

31

^CKPWRGD_PD#

IN

Input notifies device to sample latched inputs and start up on first high

assertion. Low enters Power Down Mode, subsequent high assertions exit

Power Down Mode. This pin has internal pull-up resistor.

32

^SADR_tri

LATCHED

IN

Tri-level latch to select SMBus Address. See SMBus Address Selection

Table.

33

EPAD

GND

Connect ePAD to ground.