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9DBU0241 Datasheet(PDF) 7 Page - Integrated Circuit Systems |
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9DBU0241 Datasheet(HTML) 7 Page - Integrated Circuit Systems |
7 / 17 page REVISION C 04/22/15 7 2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS 9DBU0241 DATASHEET Electrical Characteristics–DIF Low-Power HCSL Outputs Electrical Characteristics–Current Consumption TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES dV/dt Scope averaging on, fast setting (100MHz) 1 2.4 3.5 V/ns 1,2,3 dV/dt Scope averaging on, slow setting (100MHz) 0.7 1.7 2.5 V/ns 1,2,3 Slew rate matching ΔdV/dt Slew rate matching, Scope averaging on 9 20 % 1,2,4 Voltage High VHIGH 630 750 850 7 Voltage Low VLOW -150 26 150 7 Max Voltage Vmax 763 1150 7 Min Voltage Vmin -300 22 7 Vswing Vswing Scope averaging off 300 1448 mV 1,2 Crossing Voltage (abs) Vcross_abs Scope averaging off 250 390 550 mV 1,5 Crossing Voltage (var) Δ-Vcross Scope averaging off 11 140 mV 1,6 2 Measured from differential waveform 7 At default SMBus settings. Slew rate Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) mV Measurement on single ended signal using absolute value. (Scope averaging off) mV 1Guaranteed by design and characterization, not 100% tested in production. 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES IDDR VDDR @100MHz 3 6 mA 1 IDDDIG VDDIG, All outputs @100MHz 0.125 0.25 mA 1 IDDAO VDDA+VDDO, PLL Mode, All outputs @100MHz 13 17 mA 1 IDDRPD VDDR, CKPWRGD_PD# = 0 0.1 0.3 mA 1,2,3 IDDDIGPD VDDDIG, CKPWRGD_PD# = 0 0.1 0.2 mA 1,2 IDDAOPD VDDA+VDDO, CKPWRGD_PD# = 0 0.7 1 mA 1,2 1 Guaranteed by design and characterization, not 100% tested in production. 2 Input clock stopped. 3 In bypass mode, the PLL is off and IDDAO is ~50% of this value. Operating Supply Current Powerdown Current |
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