8

Figure 6b. Recommended AC coupled interface circuit

The AFCT-5963TLZ/TGZ/ATLZ/ATGZ/NLZ/NGZ have a

transmit disable function which is a single-ended +3.3 V

TTL input which is DC-coupled to pin 8.

As for the receiver section, it is internally AC-coupled

between the preamplifier and the postamplifier stages.

The actual Data and Data-bar outputs of the post-

amplifier are DC-coupled to their respective output pins

(pins 4, 5). The two data outputs of the receiver should be

terminated with identical load circuits.

Signal Detect is a single-ended, +3.3 V TTL output signal

that is DC-coupled to pin 3 of the module. Signal Detect

should not be AC-coupled externally to the follow-on

circuits because of its infrequent state changes.

Power Supply Filtering and Ground Planes

It is important to exercise care in circuit board layout to

achieve optimum performance from these transceivers.

Figures 6a and 6b show the power supply circuit

which complies with the small form factor multisource

agreement. It is further recommended that a continuous

ground plane be provided in the circuit board directly

under the transceiver to provide a low inductance ground

for signal return current. This recommendation is in

keeping with good high frequency board layout practices.

Package footprint and front panel considerations

The Avago Technologies transceivers comply with the

circuit board “Common Transceiver Footprint” hole

pattern defined in the current multisource agreement

which defined the 2 x 5 package style. This drawing is

reproduced in Figure 7 with the addition of ANSI Y14.5M

compliant dimensioning to be used as a guide in the me-

chanical layout of your circuit board. Figure 8 shows the

front panel dimensions associated with such a layout.

Eye Safety Circuit

For an optical transmitter device to be eye-safe in the

event of a single fault failure, the transmitter must either

maintain eye-safe operation or be disabled.

The AFCT-5963TLZ/TGZ/ATLZ/ATGZ/NLZ/NGZ is intrinsi-

cally eye safe and does not require shut down circuitry.

Z = 50

Ω

Z = 50

Ω

Z = 50

Ω

Z = 50

Ω

SD

LVTTL

V

V

RD+

RD-

Z = 50

Ω

1

1 µH

C2

1 µH

C1

C3

10 µF

T

X

R

X

130

Ω

130

Ω

130

Ω

130

Ω

100 nF

100 nF

100 nF

100 nF

82

Ω

130

Ω

V

130

Ω

82

Ω

T

2

3

4 5

10

9

8

7

6

TD-

TD+

Note: C1 = C2 = C3 = 10 nF or 100 nF

Note A: CIRCUIT ASSUMES OPEN EMITTER OUTPUT

Note B: WHEN INTERNAL BIAS IS PROVIDED REPLACE SPLIT RESISTORS WITH 100 WTERMINATION

* C4 AND C5 ARE OPTIONAL BYPASS CAPACITORS FOR ADDITIONAL LOW FREQUENCY NOISE FILTERING.

NOTE A

NOTE B

V

100 nF

100 nF

82

Ω

130

Ω

V

82

Ω

130

Ω

C4 *

10 µF

C5 *

10 µF