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AFCT-5815BZ Datasheet(PDF) 3 Page - AVAGO TECHNOLOGIES LIMITED |
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AFCT-5815BZ Datasheet(HTML) 3 Page - AVAGO TECHNOLOGIES LIMITED |
3 / 10 page 3 Figure 3. Recommended Circuit Schematic NO INTERNAL CONNECTION NO INTERNAL CONNECTION TOP VIEW Rx V EER 1 RD 2 SD 4 Rx V CCR 5 Tx V CCT 6 TD 8 Tx V EET 9 TERMINATE AT PHY DEVICE INPUTS V cc FILTER AT V cc PINS TRANSCEIVER V CC C2 C1 L1 L2 TD RD 3 TD 7 R8 RD RD V CC R5 R7 R6 C6 SD R10 C7 C8 C3 C4 R4 V CC R2 R3 R1 TERMINATION AT TRANSCEIVER INPUTS TD C5 R9 Recommended Circuit Schematic In order to ensure proper functionality of the AFCT‑5815xZ a recommended circuit is provided in Figure 3. When de‑ signing the circuit interface, there are a few fundamental guidelines to follow. For example, in the Recommended Circuit Schematic figure the differential data lines should be treated as 50 ohm Microstrip or stripline transmission lines. This will help to minimize the parasitic inductance and capacitance effects. Proper termination of the dif‑ ferential data signals will prevent reflections and ringing which would compromise the signal fidelity and gener‑ ate unwanted electrical noise. Locate termination at the received signal end of the transmission line. The length of these lines should be kept short and of equal length. For the high speed signal lines, differential signals should be used, not single‑ended signals, and these differential signals need to be loaded symmetrically to prevent un‑ balanced currents from flowing which will cause distor‑ tion in the signal. Maintain a solid, low inductance ground plane for re‑ turning signal currents to the power supply. Multilayer plane printed circuit board is best for distribution of VCC, returning ground currents, forming transmission lines and shielding, Also, it is important to suppress noise from influencing the fiber‑optic transceiver performance, especially the receiver circuit. Proper power supply filtering of VCC for this transceiver is accomplished by using the recommended, separate filter circuits shown in Figure 3 for the transmitter and receiver sections. These filter circuits suppress VCC noise over a broad frequency range, this prevents receiver sensitivity degradation due to VCC noise. It is recommended that surface‑mount components be used. Use tantalum capacitors for the 10 µF capacitors and monolithic, ceramic bypass capaci‑ tors for the 0.1 µF capacitors. Also, it is recommended that a surface‑ mount coil inductor of 3.3 µH be used. Ferrite beads can be used to replace the coil inductors when using quieter VCC supplies, but a coil inductor is recommended over a ferrite bead. All power supply components need to be placed physically next to the VCC pins of the receiver and transmitter. Use a good, uni‑ form ground plane with a minimum number of holes to provide a low‑inductance ground current return for the power supply currents. In addition to these recommendations, Avago Tech‑ nologies Application Engineering staff is available for consulting on best layout practices with various vendors mux/demux, clock generator and clock recovery circuits. Avago Technologies has participated in several reference design studies and is prepared to share the findings of these studies with interested customers. Contact your local Avago Technologies sales representative to arrange for this service. NOTES: THE SPLIT‑LOAD TERMINATIONS FOR PECL SIGNALS NEED TO BE LOCATED AT THE INPUT OF DEVICES RECEIVING THOSE PECL SIGNALS. RECOMMEND 4‑LAYER PRINTED CIRCUIT BOARD WITH 50 Ω MICROSTRIP SIGNAL PATHS BE USED. FOR +5.0V AND +3.3V OPERATION. R1 = R4 = R6 = R8 = R10 = 130 Ω R2 = R3 = R5 = R7 = R9 = 82 Ω C1 = C2 = 10 µF C3 = C4 = C7 = C8 = 100 nF C5 = C6 = 0.1 µF L1 = L2 = 3.3 µH COIL OR FERRITE INDUCTOR. |
Similar Part No. - AFCT-5815BZ_15 |
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Similar Description - AFCT-5815BZ_15 |
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