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ABCU-5741AGZ Datasheet(PDF) 11 Page - AVAGO TECHNOLOGIES LIMITED |
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ABCU-5741AGZ Datasheet(HTML) 11 Page - AVAGO TECHNOLOGIES LIMITED |
11 / 25 page 11 Table 4. Summary of Internal IC Registers Register Description 0 Control 1 Status 2-3 N/A for SFP Module 4 Auto-Negotiation Advertisement 5 Auto-Negotiation Link Partner Ability 6 Auto-Negotiation Expansion 7 Auto-Negotiation Next Page Transmit 8 Auto-Negotiation Link Partner Received Next Page 9 MASTER-SLAVE Control Register 10 MASTER-SLAVE Status Register 11-15 N/A for SFP Module 16 Extended Control 1 17 Extended Status 1 18-19 N/A for SFP Module 20 Extended Control 2 21 Receive Error Counter 22 Cable Diagnostic 1 23-25 N/A for SFP Module 26 Extended Control 3 27 Extended Status 2 28 Cable Diagnostic 2 29-31 N/A for SFP Module Internal ASIC Registers The ASIC (or “PHY”, for Physical Layer IC) in the trans- ceiver module contains 32 registers. Each register contains 16 bits. The registers are summarized in table 11 and detailed in table 12 through 28. Each bit is either Read Only (RO) or Read/Write (R/W). Some bits are also described as Latch High (LH) or Latch Low (LL) and/or Self Clearing (SC). The registers are accessible through the 2-wire se- rial CMOS EEPROM protocol of the ATMEL AT24C01A or equivalent. The address of the PHY is 1010110x, where x is the R/W bit. Each register’s address is 000yyyyy, where yyyyy is the binary equivalent of the register number. Write and read operations must send or receive 16 bits of data, so the “multi-page” access protocol must be used. |
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