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AFBR-775BEPZ Datasheet(PDF) 8 Page - AVAGO TECHNOLOGIES LIMITED |
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AFBR-775BEPZ Datasheet(HTML) 8 Page - AVAGO TECHNOLOGIES LIMITED |
8 / 48 page 8 Recommended Operating Conditions Recommended Operating Conditions specify parameters for which the optical and electrical characteristics hold unless otherwise noted. Optical and electrical characteristics are not defined for operation outside the Recommend- ed Operating Conditions, reliability is not implied and damage to the module may occur for such operation over an extended period of time. Parameter Symbol Min Typ Max Units Reference Case Temperature Tc 0 40 80 °C 2.5 V Power Supply Voltage Vcc25 2.375 2.5 2.625 V Figures 12, 13 3.3 V Power Supply Voltage Vcc33 3.135 3.3 3.465 V Figures 12, 13 Signal Rate per Channel 2.5 5.0 GBd Data Input Differential Peak-to-Peak Voltage Swing ΔVDI pp 175 1400 mVpp 3, Figure 14 Data Input Common Mode Voltage VDI CM 0.35 Vcc33-0.35 V 4 Data Input Rise & Fall Times (20% - 80%) 30 48 ps Data Input Deterministic Jitter 32 ps 5 Data Input Total Jitter 66 ps 6 Control* Input Voltage High Vih 2 Vcc33 V Control* Input Voltage Low Vil GND 0.8 V Two Wire Serial Interface Clock Rate 400 kHz Figure 17 Reset Pulse Width tRSTL PW 10 µs Figure 19 Power Supply Noise 100 mVpp 7500 Hz to 2.7 GHz Receiver Differential Data Output Load 100 Ohms Figure 3 AC Coupling Capacitors – Receiver Data Outputs Cac 0.1 µF 8, Figure 3 Fiber Length: 500 MHz∙km 50µm MMF 0.5 75 m 9 Fiber Length: 2000 MHz∙km 50µm MMF 0.5 150 m Notes: * Control signals, LVTTL (3.3 V) compatible, include Adr[2:0], IntL, ResetL, SCL and SDA. 1 The position for case temperature measurement is shown in Figure 11. Continuous operation at the maximum Recommended Operating Case Temperature should be avoided in order not to degrade reliability. Modules will function (degraded performance may result) where operated with case temperatures below the minimum Recommended Operating Case Temperature. 2. While operation for various codes, e.g. 8b10b, are supported, certain parameters, jitter and sensitivity, are defined for specific operating conditions of 5.0 GBd and 8b10b equivalent test patterns. The receiver has a low frequency -3dB corner near 100 kHz. 3. Data inputs are CML compatible. Minimum input requirement holds for default input equalization settings. Data Input Differential Peak to Peak Voltage Swing is defined as follows: ΔVDI pp = ΔVDIH – ΔVDIL where ΔVDIH = High State Differential Data Input Voltage and ΔVDIL = Low State Differential Data Input Voltage. 4. Data Input Common Mode Voltage is defined as follows: VDICM = (VDinp + VDinn)/2. 5. Deterministic Jitter, DJ, conforms to the dual-Dirac model where TJ(BER) = DJ + 2Q(BER)RJrms and RJrms is the width of the Gaussian component. Here BER = 10-12. DJ is measured with the same conditions as TJ. Effects of impairments in the test signal due to the test system are removed from the measurement. All channels not under test are operating with similar test patterns. 6. Total Jitter, TJ, defined for a BER of 10-12, is measured at the 50% signal level using a 5.0 GBd Pseudo Random Bit Sequence of length 27-1 (PRBS7), or equivalent, test pattern. Effects of impairments in the test signals due to the test system are removed from the measurement. All channels not under test are operating with similar test patterns. 7. Power Supply Noise is defined as the peak-to-peak noise amplitude over the frequency range at the host supply side of the recommended power supply filter with the module and recommended filter in place. Voltage levels including peak-to-peak noise are limited to the recommended operating range of the associated power supply. See Figures 12 and 13 for recommended power supply filters. 8. For data pattern with restricted run lengths and disparity, e.g. 8b10b, smaller value capacitors may provide acceptable results. 9. Channel insertion loss includes 3.5 dB/km attenuation, 1.5 dB connector loss and 0.3 dB modal noise penalty allocations. |
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