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AFBR-775BZ Datasheet(PDF) 3 Page - AVAGO TECHNOLOGIES LIMITED |
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AFBR-775BZ Datasheet(HTML) 3 Page - AVAGO TECHNOLOGIES LIMITED |
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3 / 48 page  3 ASIC/SerDes FO Tx (1 of 12 Lanes) Host Board Electrical Interface - Compliance Points - FO Rx Electrical Interface FO Rx (1 of 12 Lanes) FO Tx Electrical Interface S DD22 S CC22 S CC11 S DD11 S CD11 S DC22 C AC C AC 50 Ω 50 Ω 50 Ω 50 Ω Figure 3. Application Reference Diagram Frequency No Equalization Maximum Equalization Figure 4. Input Equalization High Speed Signal Interface Figure 3 shows the interface between an ASIC/SerDes and the fiber optics modules. For simplicity, only one channel is shown. As shown in the Figure 3, the compliance points are on the host board side of the electrical connec- tors. Sets of s-parameters are defined for the transmit- ter and receiver interfaces. The transmitter and receiver are designed, when operating within Recommended Operating Conditions, to provide a robust eye-opening at the receiver outputs. See the Recommended Operating Conditions and the Receiver Electrical Characteristics for details. Unused inputs and outputs should be terminated with 100 Ω differential loads. The transmitter inputs support a wide common mode range and DC blocking capacitors may not be needed – none are shown in Figure 3. Depending on the common mode range tolerance of the ASIC/SerDes inputs, DC blocking capacitors may be required in series with the receiver. Differential impedances are nominally 100 Ω. The common mode output impedance for the receiver is nominally 25 Ω while the nominal common mode input impedance of the transmitter is 25 Ω. Transmitter Input Equalization Transmitter inputs can be programmed for one of several levels of equalization. See Figure 4. The default case provides a flat gain-frequency response in the inputs. Different levels of compensation can be selected to equalize skin-effect losses across the host circuit board. See Tx Memory Map 01h Upper Page section addresses 228 - 233 for programming details. resumes. All interrupts can be masked and flags are reset upon reading the appropriate flag register. The elec- trical output will squelch for loss of input signal (unless squelch is disabled) and channel de-activation through TWS interface. Status and alarm information are available via the TWS interface. The interrupt signal (selectable via the TWS interface as a pulse or static level) is provided to inform hosts of an assertion of an alarm and/or LOS. |
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