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MAX198AENI Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX198AENI Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 16 page Input Capacitance Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface 4 _______________________________________________________________________________________ ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) V 2.4 4.18 Input Voltage Range µA 400 Input Current VREF = 4.18V 1 V VDD - 50mV REFADJ Threshold for Buffer Disable Normal, or STANDBY power-down mode k Ω 10 Input Resistance FULL power-down mode 5 M Ω Normal, or STANDBY power-down mode FULL power-down mode Internal acquisition 3.0 5.0 External reference = 4.096V After FULLPD or STBYPD External acquisition (Note 9) CONDITIONS FULL power-down mode (Note 7) 5 µs 3.0 tACQI Acquisition Time LSB ±0.1 ±1/2 PSRR Power-Supply Rejection Ratio (Note 8) 3.0 tACQE External CLK µs V 4.75 5.25 VDD Supply Voltage 6.0 tCONV Conversion Time Internal CLK, CCLK = 100pF 6.0 7.7 10.0 To 0.1mV REF bypass capacitor fully discharged ms 8 Reference Buffer Settling 60 120 60 Normal mode, bipolar ranges 700 850 Normal mode, unipolar ranges UNITS MIN TYP MAX SYMBOL PARAMETER STANDBY power-down mode mA 18 IDD Supply Current 610 µA Internal reference ±1/2 CCLK = 100pF MHz 1.25 1.56 2.00 fCLK Internal Clock Frequency 0.1 2.0 fCLK External Clock Frequency Range MHz External CLK Internal CLK Power-up (Note 10) µs 200 Bandgap Reference Start-Up Time External CLK ksps 100 Throughput Rate Internal CLK, CCLK = 100pF 62 CREF = 4.7µF CREF = 33µF CIN 15 pF (Note 5) Input Leakage Current IIN ±10 µA VIN = 0V or VDD Input Low Voltage VINL 0.8 V Input High Voltage VINH 2.4 V POWER REQUIREMENTS TIMING REFERENCE INPUT (buffer disabled, reference input applied to REF pin) DIGITAL INPUTS (D7–D0, CLK, RD, WR, CS) (Note 11) |
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