If the power supplies do not settle within the MAX195’s

power-on delay (500ns minimum), power-up calibration

may begin with supply voltages that differ from the final

values and the converter may not be properly calibrat-

ed. If so, recalibrate the converter (pulse RESET low)

before use. For best DC accuracy, calibrate the

MAX195 any time there is a significant change in sup-

ply voltages, temperature, reference voltage, or clock

characteristics (see

External Clock section) because

these parameters affect the DC offset. If linearity is the

only concern, much larger changes in these parame-

ters can be tolerated.

Because the calibration data is stored digitally, there is

no need either to perform frequent conversions to main-

tain accuracy or to recalibrate if the MAX195 has been

held in shutdown for long periods. However, recalibra-

tion is recommended if it is likely that ambient tempera-

ture or supply voltages have significantly changed

since the previous calibration.

Digital Interface

The digital interface pins consist of BP/UP/SHDN, CLK,

SCLK, EOC, CS, CONV, and RESET.

BP/UP/SHDN is a three-level input. Leave it floating to

configure the MAX195’s analog input in bipolar mode

places the MAX195 in its 10µA shutdown mode.

A logic low on RESET halts MAX195 operation. The ris-

ing edge of RESET initiates calibration as described in

the

Calibration section above.

Begin a conversion by bringing CONV low. After con-

version begins, additional convert start pulses are

ignored. The convert signal must be synchronized with

CLK. The falling edge of CONV must occur during the

period shown in Figures 3 and 4. When CLK is not

directly controlled by your processor, two methods of

ensuring synchronization are to drive CONV from EOC

(continuous conversions) or to gate the conversion-start

signal with the conversion clock so that CONV can go

low only while CLK is low (Figure 5). Ensure that the

maximum propagation delay through the gate is less

than 40ns.

The MAX195 automatically ensures four CLK periods

for track/hold acquisition. If, when CONV is asserted, at

least three clock (CLK) cycles have passed since the

end of the previous conversion, a conversion will begin

on CLK’s next falling edge and EOC will go high on the

following falling CLK edge (Figure 3). If, when convert

is asserted, less than three clock cycles have passed,

a conversion will begin on the fourth falling clock edge

16-Bit, 85ksps ADC with 10µA Shutdown

_______________________________________________________________________________________

7

TRACK/HOLD

CLK

CONVERSION

BEGINS

CONVERSION

ENDS

*

EOC

CONV

Figure 3. Initiating Conversions—At least 3 CLK cycles since end of previous conversion.