CDMA Cellular/PCS System

Power Supplies

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7

Note 2: Specifications to -40°C are guaranteed by design, not production tested.

Note 3: Specifications are guaranteed by design, not production tested in the EGP (QFN) package.

CONDITIONS

SCLK Clock Frequency

2

MHz

SCLK Low Period

125

ns

SCLK High Period

125

ns

Data Hold Time

0

ns

Data Setup Time

125

ns

CS Assertion to SCLK Rising

Edge Setup Time

200

ns

CS Deassertion to SCLK Rising

Edge Setup Time

200

ns

SCLK Rising Edge to CS

Deassertion

200

ns

SCLK Rising Edge to CS

Assertion

200

ns

CS High Period

300

ns

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

ELECTRICAL CHARACTERISTICS (continued)

open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,

SPI TIMING (MAX1798/MAX1798A)

OUTPUT VOLTAGE ACCURACY (OUT1)

vs. LOAD CURRENT

-2.0

-1.0

-1.5

0

-0.5

1.5

1.0

0.5

2.0

0

100

50

150

200

250

300

LOAD CURRENT (mA)

OUTPUT VOLTAGE ACCURACY (OUT2–5)

vs. LOAD CURRENT

-2.0

-1.0

-1.5

0

-0.5

1.5

1.0

0.5

2.0

050

25

75

100

125

150

LOAD CURRENT (mA)

-2.0

-1.0

-1.5

0

-0.5

1.5

1.0

0.5

2.0

-40

10

-15

35

60

85

OUTPUT VOLTAGE ACCURACY (OUT1)

vs. TEMPERATURE

TEMPERATURE (°C)

Typical Operating Characteristics