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TB62747AFG Datasheet(PDF) 6 Page - Marktech Corporate

Part # TB62747AFG
Description  TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
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Manufacturer  MARKTECH [Marktech Corporate]
Direct Link  http://www.marktechopto.com
Logo MARKTECH - Marktech Corporate

TB62747AFG Datasheet(HTML) 6 Page - Marktech Corporate

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TB62747AFG/AFNG/AFNAG/BFNAG
2009-01-21
6
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating *1
Unit
Power supply voltage
VDD
−0.4 to 6.0
V
Output current
IO
55
mA
Logic input voltage
VIN
−0.3 to VDD + 0.3 *2
V
Output voltage
VO
−0.3 to 26
V
Operating temperature
Topr
−40 to 85
°C
Storage temperature
Tstg
−55 to 150
°C
Thermal resistance
Rth(j-a)
94 (AFG) *3, 120 (AFNG) *3, 80.07(AFNAG/BFNAG)
When mounted PCB
°C/W
Power dissipation
PD*4
1.32 (AFG) *3, 1.04 (AFNG) *3, 1.56(AFNAG/BFNAG)
When mounted PCB
W
Note1: Voltage is ground referenced.
Note2: However, do not exceed 6V.
Note3: PCB condition 76.2 x 114.3 x 1.6 mm, Cu 30% (SEMI conforming)
Note4: The power dissipation decreases the reciprocal of the saturated thermal resistance (1/ Rth(j-a)) for each
degree (1°C) that the ambient temperature is exceeded (Ta = 25°C).
Operating Conditions
DC Items (Unless otherwise specified, VDD = 3.0 to 5.5 V, Ta = −40°C to 85°C)
Characteristics
Symbol
Test Conditions
Min
Typ.
Max
Unit
Power supply voltage
VDD
3.0
5.5
V
Output voltage when OFF
VO (ON)
OUTn
0.4
4.0
V
High level logic input voltage
VIH
SIN,SCK, SLAT , OE
0.7
×
VDD
VDD
V
Low level logic input voltage
VIL
SIN,SCK, SLAT , OE
GND
0.3
×
VDD
V
High level SOUT output current
IOH
−1
mA
Low level SOUT output current
IOL
1
mA
IO1
OUTn , VDD = 3.3 V, VO = 0.4 to 1.0 V
1.5
35
Constant current output
IO2
OUTn , VDD = 5.0 V, VO = 0.4 to 1.2 V
1.5
45
mA
AC Items (Unless otherwise specified, VDD = 3.0 to 5.5 V, Ta = −40°C to 85°C)
Characteristics
Symbol
Test
Circuits
Test Conditions
Min
Typ.
Max
Unit
Serial data transfer frequency
fSCK
6
25
MHz
tHOLD1
6
5
ns
Hold time
tHOLD2
6
5
ns
tSETUP1
6
5
ns
Setup time
tSETUP2
6
5
ns
Maximum clock rise time
tr
6
*1
500
ns
Maximum clock fall time
tf
6
*1
500
ns
Note1: If the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock
waveform,it may not be possible to achieve the timing required for data transfer. Please keep these timing conditions in mind
when designing your application.


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