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MAX1718BEEI Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX1718BEEI Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 35 page Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning (IMVP-II) 10 ______________________________________________________________________________________ Pin Description (continued) Supply Voltage Input for the DL Gate Driver, 4.5V to 5.5V. Bypass to GND with a 1µF capacitor. VDD 17 Low-Side Gate Driver Output. DL swings GND to VDD. DL 16 Analog and Power Ground. Also connects to the current-limit comparator. GND 15 Open-Drain Power-Good Output. VGATE is normally high when the output is in regulation. If VFB is not within a ±10% window of the DAC setting, VGATE is asserted low. During DAC code transitions, VGATE is forced high until 1 clock period after the slew-rate controller finishes the transition. VGATE is low during shutdown. VGATE 14 Feedback Offset Adjust Negative Input. The output shifts by an amount equal to the difference between POS and NEG multiplied by a scale factor that depends on the DAC codes (see the Integrator Amplifiers/Output Voltage Offsets section). Connect both POS and NEG to REF if the offset function is not used. POS 13 Current-Limit Adjustment. The GND - LX current-limit threshold defaults to 100mV if ILIM is connected to VCC. In adjustable mode, the current-limit threshold voltage is 1/10th the voltage seen at ILIM over a 0.5V to 3V range. The logic threshold for switchover to the 100mV default value is approximately VCC - 1V. Connect ILIM to REF for a fixed 200mV threshold. ILIM 12 2V Reference Output. Bypass to GND with 0.22µF (min) capacitor. Can source 50µA for external loads. Loading REF degrades FB accuracy according to the REF load-regulation error. REF 11 On-Time Selection Control Input. This is a four-level input that sets the K factor (Table 2) to determine DH on-time. Connect TON to the following pins for the indicated operation: GND = 1000kHz REF = 550kHz Open = 300kHz VCC = 200kHz TON 10 PIN NAME FUNCTION Suspend-Mode Control Input. When SUS is high, the suspend-mode VID code, as programmed by S0 and S1, is delivered to the DAC. Connect SUS to GND if the Suspend-mode multiplexer is not used (see the Internal Multiplexers (ZMODE/SUS) section). SUS 18 Performance-Mode MUX Control Input. If SUS is low, ZMODE selects between two different VID DAC codes. If ZMODE is low, the VID DAC code is set by the logic-level voltages on D0–D4. On the rising edge of ZMODE, during power-up with ZMODE high, or on the falling edge of SUS when ZMODE is high, the VID DAC code is determined by the impedance at D0–D4 (see the Internal Multiplexers (ZMODE/SUS) section). ZMODE 19 Overvoltage Protection Control Input. Connect OVP low to enable overvoltage protection. Connect OVP high to disable overvoltage protection. The overvoltage trip threshold is approximately 2V. The state of OVP does not affect output undervoltage fault protection or thermal shutdown. OVP 20 VID DAC Code Inputs. D0 is the LSB, and D4 is the MSB of the internal 5-bit VID DAC (Table 3). If ZMODE is low, D0–D4 are high-impedance digital inputs, and the VID DAC code is set by the logic-level voltages on D0–D4. On the rising edge of ZMODE, during power-up with ZMODE high, or on the falling edge of SUS when ZMODE is high, the VID DAC code is determined by the impedance at D0–D4 as follows: Logic low = source impedance is ≤1kΩ + 5%. Logic high = source impedance is ≥100kΩ - 5%. D4–D0 21–25 Boost Flying Capacitor Connection. Connect BST to the external boost diode and capacitor as shown in Figure 1. An optional resistor in series with BST allows the DH pullup current to be adjusted (Figure 8). BST 26 Inductor Connection. LX is the internal lower supply rail for the DH high-side gate driver. It also connects to the current-limit comparator and the skip-mode zero-crossing comparator. LX 27 High-Side Gate-Driver Output. DH swings LX to BST. DH 28 |
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