+2.7V, Low-Power, 2-Channel,

108ksps, Serial 10-Bit ADCs in 8-Pin µMAX

4

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ELECTRICAL CHARACTERISTICS (continued)

TIMING CHARACTERISTICS (Figure 7)

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been

calibrated.

Note 3: Offset nulled.

Note 4: The on channel is grounded; the sine wave is applied to off channel (MAX157 only).

Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.

Note 7: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.

Note 8: Guaranteed by design. Not subject to production testing.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

05

SCLK Clock Frequency

0.1

2.17

MHz

SCLK Fall to Output Data Valid

20

120

ns

215

CS/SHDN Fall to Output Enable

Wake-Up Time

2.5

µs

120

ns

CS/SHDN Rise to Output

Disable

120

ns

SCLK Pulse Width High

50

ns

CONDITIONS

Internal clock, SCLK for data transfer only

(Note 8)

Internal clock, SCLK for data transfer only

External clock

External clock

ns

SCLK to CS/SHDN Setup

60

CS/SHDN Pulse Width

60

ns

215

SCLK Pulse Width Low

50

ns

Internal clock, SCLK for data transfer only

(Note 8)

External clock

POWER REQUIREMENTS

Power-Supply Rejection

(Note 9)

PSR

±0.15

mV

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Positive Supply Voltage

+2.7

+5.25

V

CONDITIONS

Positive Supply Current

0.9

2.0

mA

Operating mode

Positive Supply Current

0.2

5

µA

Shutdown, CS/SHDN = GND

POWER REQUIREMENTS