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MAX152CPP Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX152CPP Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 12 page _________________________________________________________________________________________ +3V, 8-Bit ADC with 1µA Power-Down 4 _______________________________________________________________________________________ PARAMETER SYMBOL CONDITIONS MAX152C/E TA = TMIN to TMAX MIN MAX MAX152M TA = TMIN to TMAX MIN MAX UNITS WR Pulse Width tWR 0.6 10 0.66 10 0.8 10 µs Delay Time Between WR and RD Pulses tRD 0.8 0.9 1.0 µs RD Pulse Width tREAD1 400 500 600 ns tACC1 400 500 600 ns RD to INT Delay tRI 300 340 400 ns tCWR tRD < tINTL, CL = 100pF 1.8 2.06 2.4 µs Conversion Time (RD Mode) tCRD 2.0 2.3 2.6 µs Power-Up Time tUP 0.9 1.2 1.4 µs CS to RD,WR Setup Time tCSS 0 0 0 ns CS to RD,WR Hold Time tCSH 0 0 0 ns CS to RDY Delay tRDY CL = 50pF, RL = 5.1kΩ to VDD 100 120 140 ns WR to INT Delay tINTL CL = 50pF 0.7 1.45 1.6 1.8 RD Pulse Width tREAD2 WR-RD mode, tRD > tINTL, determined by tACC2 (Figure 5) 180 220 250 ns Data Access Time (Note 7) tACC2 180 220 250 ns WR to INT Delay tIHWR 180 200 240 ns Data Access Time After INT (Note 7) tID Stand-alone mode, CL = 100pF 100 130 150 ns Data Access Time (RD Mode) (Note 7) tACC0 CL = 100pF tCRD +100 tCRD +150 ns RD to INT Delay (RD Mode) tINTH CL = 50pF 100 160 170 180 ns Data Hold Time (Note 8) tDH 100 130 150 ns tP 450 600 700 ns ALL GRADES TA = +25°C MIN TYP MAX Conversion Time (WR-RD Mode) Delay Time Between Conversions Data Access Time (Note 7) WR-RD mode, determined by tACC1 (Figure 6) WR-RD mode, tRD < tINTL, CL = 100pF (Figure 6) WR-RD mode, tRD < tINTL , CL = 100pF (Figure 5) tCRD +130 µs TIMING CHARACTERISTICS (Unipolar input range, VDD = 3V, VSS = 0V, TA = +25°C, unless otherwise noted.) (Note 6) Note 6: Input control signals are specified with tr = tf = 5ns, 10% to 90% of +3.0V, and timed from a voltage level of 1.3V. Timing delays get shorter at higher supply voltages. See the Converson Time vs. Supply Voltage graph in the Typical Operating Characteristics to extrapolate timing delays at other power-supply voltages. Note 7: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.66V or 2.0V. Note 8: See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V. Stand-alone mode, CL = 50pF |
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