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MAX1458AAE Datasheet(PDF) 8 Page - Maxim Integrated Products

Part # MAX1458AAE
Description  1%-Accurate, Digitally Trimmed Sensor Signal Conditioner
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1458AAE Datasheet(HTML) 8 Page - Maxim Integrated Products

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• Configuration register (Table 3)
• 12-bit calibration coefficients for the Offset and FSO
DACs
• 12-bit compensation coefficients for the Offset TC
and FSOTC DACs
• Two general-purpose registers available to the user
for storing process information such as serial num-
ber, batch date, and check sums
Program the EEPROM one bit at a time. The bits have
addresses from 0 to 127 (7F hex).
Configuration Register
The configuration register (Table 3) determines the
PGA gain, the polarity of the offset and offset TC coeffi-
cients, and the coarse offset correction (IRO DAC). It
also enables/disables internal resistors (RFTC and
RISRC).
DAC Registers
The Offset, Offset TC, FSO, and FSOTC registers store
the coefficients used by their respective calibration/
compensation DACs.
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
8
_______________________________________________________________________________________
Table 4. EEPROM Memory Map
EE Address
Contents
EE Address
Contents
EE Address
Contents
EE Address
Contents
EE Address
Contents
Reserved*
EE Address
Contents
EE Address
Contents
0E
0
0C
0
0F
0D
0
0A
08
0B
09
06
04
07
05
02
1
00
Configuration
03
01
1E
0
1C
1
1F
1D
0
1A
18
1B
19
16
14
17
15
12
1
10
MSB
Offset
LSB
13
11
2E
0
2C
0
2F
2D
1
2A
28
2B
29
26
24
27
25
22
1
20
MSB
Offset TC
LSB
23
21
3E
0
3C
1
3F
3D
1
3A
38
3B
39
36
34
37
35
32
1
30
MSB
FSO
LSB
33
31
4E
1
4C
0
4F
4D
0
4A
48
4B
49
46
44
47
45
42
1
40
MSB
FSOTC
LSB
43
41
5E
0
5C
0
5F
5D
0
5A
58
5B
59
56
54
57
55
52
0
50
0
53
51
6E
0
6C
0
6F
6D
0
6A
68
6B
69
66
64
67
65
62
0
60
User defined bits
63
61
7E
0
7C
0
7F
7D
0
7A
78
7B
79
76
74
77
75
72
0
70
User defined bits
73
71
Note: The MAX1458 processes the Reserved Bits in the EEPROM. If these bits are not properly programmed, the configuration
and DAC registers will not be updated correctly.
* The contents of the Reserved EE Address 50–5F must all be reset to zero.
= Reserved Bits
0
0
0
0
0
0
0
0
0
0
0


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