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MAX1450 Datasheet(PDF) 5 Page - Maxim Integrated Products

Part No. MAX1450
Description  Low-Cost, 1%-Accurate Signal Conditioner for Piezoresistive Sensors
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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Summing Junction
The second stage in the analog signal path consists of
a summing junction for offset, offset temperature com-
pensation, and the PGA output. The offset voltage
(VOFFSET) and offset temperature-compensation volt-
age (VOFFTC) add or subtract from the PGA output
depending on their respective sign bits, offset sign
(SOFF), and offset TC sign (SOTC). VOFFSET and
VOFFTC can range in magnitude from VSS to VDD.
Output Buffer
The final stage in the analog signal path consists
of a unity-gain buffer. This buffer is capable of swinging
to within 250mV of VSS and VDD while sourcing/sinking
up to 1.0mA, or within 50mV of the power supplies with
no load.
Bridge Drive
Figure 2 shows the functional diagram of the on-chip
current source. The voltage at FSOTRIM, in conjunction
with RISRC, sets the nominal current, IISRC which sets
the FSO (refer to Figure 3 for sensor terminology.) IISRC
is additionally modulated by components from the
external resistor RSTC and the optional resistor RLIN.
RSTC is used to feed back a portion of the buffered
bridge-excitation voltage (VBBUF), which compensates
FSO TC errors by modulating the bridge-excitation cur-
rent over temperature. To correct FSO linearity errors,
feed back a portion of the output voltage to the current-
source reference node via the optional RLIN resistor.
Applications Information
Compensation Procedure
The following compensation procedure assumes a pres-
sure transducer with a +5V supply and an output voltage
that is ratiometric to the supply voltage (see
Ratiometric
Output Configuration section). The desired offset voltage
(VOUT at PMIN) is 0.5V, and the desired FSO voltage
(VOUT(PMAX) - VOUT(PMIN)) is 4V; thus the FS output volt-
age (VOUT at PMAX) will be 4.5V. The procedure requires
a minimum of two test pressures (e.g., zero and full scale)
and two temperatures. A typical compensation procedure
is as follows:
1) Perform Coefficient Initialization
2) Perform FSO Calibration
3) Perform FSO TC Compensation
4) Perform OFFSET TC Compensation
5) Perform OFFSET Calibration
6) Perform Linearity Calibration (Optional)
Coefficient Initialization
Select the resistor values and the PGA gain to prevent
gross overload of the PGA and bridge current source.
These values depend on sensor behavior and require
some sensor characterization data. This data may be
available from the sensor manufacturer. If not, it can be
generated by performing a two-temperature, two-pres-
Low-Cost, 1%-Accurate Signal Conditioner
for Piezoresistive Sensors
_______________________________________________________________________________________
5
VDD
IBDRIVE ≈ 13 (IISRC)
VBDRIVE
IISRC
IISRC
BBUF
INP
INM
SENSOR
RISRC
(EXTERNAL)
BDRIVE
FSOTRIM
BBUF
OUT
A = 1
RSTC
(EXTERNAL)
RLIN (OPTIONAL)
(EXTERNAL)
MAX1450
Figure 2. Bridge Drive Circuit




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