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MAX1241CESA Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX1241CESA Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 16 page +2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO 8 _______________________________________________________________________________________ _______________Detailed Description Converter Operation The MAX1240/MAX1241 use an input track/hold (T/H) and successive-approximation register (SAR) circuitry to convert an analog input signal to a digital 12-bit out- put. No external-hold capacitor is needed for the T/H. Figure 3 shows the MAX1240/MAX1241 in its simplest configuration. The MAX1240/MAX1241 convert input signals in the 0V to VREF range in 9µs, including T/H acquisition time. The MAX1240’s internal reference is trimmed to 2.5V, while the MAX1241 requires an external reference. Both devices accept voltages from 1.0V to VDD. The serial interface requires only three digital lines (SCLK, CS, and DOUT) and provides an easy interface to microprocessors (µPs). The MAX1240/MAX1241 have two modes: normal and shutdown. Pulling SHDN low shuts the device down and reduces supply current below 10µA (VDD ≤ 3.6V), while pulling SHDN high or leaving it open puts the device into operational mode. Pulling CS low initiates a conver- sion. The conversion result is available at DOUT in unipolar serial format. The serial data stream consists of a high bit, signaling the end of conversion (EOC), fol- lowed by the data bits (MSB first). Analog Input Figure 4 illustrates the sampling architecture of the ana- log-to-digital converter’s (ADC’s) comparator. The full- scale input voltage is set by the voltage at REF. Track/Hold In track mode, the analog signal is acquired and stored in the internal hold capacitor. In hold mode, the T/H switch opens and maintains a constant input to the ADC’s SAR section. During acquisition, the analog input (AIN) charges capacitor CHOLD. Bringing CS low ends the acquisition interval. At this instant, the T/H switches the input side of CHOLD to GND. The retained charge on CHOLD repre- sents a sample of the input, unbalancing node ZERO at the comparator’s input. In hold mode, the capacitive digital-to-analog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 12- bit resolution. This action is equivalent to transferring a charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. At the conversion’s end, the input side of CHOLD switches back to AIN, and CHOLD charges to the input signal again. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. Acquisition time is calculated by: tACQ = 9(RS + RIN) x 16pF where RIN = 9kΩ, RS = the input signal’s source imped- ance, and tACQ is never less than 1.5µs. Source imped- ances below 1k Ω do not significantly affect the ADC’s AC performance. AIN TRACK INPUT HOLD GND TRACK HOLD 9k RIN CHOLD 16pF -+ CSWITCH COMPARATOR ZERO REF 12-BIT CAPACITIVE DAC AT THE SAMPLING INSTANT, THE INPUT SWITCHES FROM AIN TO GND. SHUTDOWN INPUT ANALOG INPUT 0V TO VREF +2.7V to +3.6V* * ** VDD,MAX = +5.25V (MAX1241) 4.7 µF (MAX1240) 0.1 µF (MAX1241) 1 2 3 4 VDD AIN SHDN REF 8 7 6 5 SCLK CS DOUT GND SERIAL INTERFACE C** 4.7 µF 0.1µF REFERENCE INPUT (MAX1241 ONLY) MAX1240 MAX1241 Figure 3. Operational Diagram Figure 4. Equivalent Input Circuit |
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