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MAX132CWG Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX132CWG Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 16 page ____________Functional Description The MAX132 integrates the input voltage for a fixed period of time, then deintegrates a known reference voltage and measures the time required to reach zero. Good line rejection is achieved by setting the (input) integration time equal to one 50Hz or 60Hz period. The MAX132 has a 50Hz/60Hz mode selection bit that sets the integration time to 655/545 clock periods, respec- tively, so that 50Hz/60Hz rejection is obtained with a 32,768Hz crystal. The MAX132 is tested and guaran- teed at a 16 conv/sec throughput rate. Figure 1 shows the basic MAX132 application circuit, with component values selected for 16 conv/sec . For applications that don’t require 50Hz/60Hz rejection, the MAX132 will operate up to 100 conv/sec at reduced accuracy (typically 0.012% FSR nonlinearity, or ±13 bits). In these applications, the 50Hz mode is recom- mended because of its longer (655 count) integration time. See Increased Speed section. __________Analog Design Procedure Input Voltage Range and Input Protection The recommended analog full-scale input range is ±512mV. Performance is tested and guaranteed at ±512mV full scale, corresponding to a 2µV/LSB resolu- tion at 18 bits. Resolution is defined as follows: which corresponds to 2µV/LSB resolution at 18 bits. Consult the Typical Operating Characteristics for Noise vs. Number of Samples Averaged and other important operating parameters. Note how accuracy depends on common-mode input voltage (common mode is defined here as |VIN LO - AGND|). For optimum performance, set the analog input full-scale between ±470mV and ±18-Bit ADC with Serial Interface 6 _______________________________________________________________________________________ Re / ( ) / , solution Volts LSB V FS IN [] = 262 144 3k 3k DOUT DOUT a. High-Z to VOH (t8) b. High-Z to VOL (t8) DGND DGND +5V CL CL Figure 3. Load Circuits for Access Time 3k 3k DOUT DOUT a. VOH to High-Z (t10) b. VOL to High-Z (t10) DGND DGND +5V 10pF 10pF Figure 4. Load Circuits for Disable Time to Three-State DIN t2 t4 t1 t3 t9 t10 t6 t8 t7 t11, t12 t5 SCLK CS DOUT P0–P3 MSB IN B6–B1 LSB IN LSB OUT B6–B1 MSB OUT Figure 2. Serial-Mode Timing |
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