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MAX128AENG Datasheet(PDF) 5 Page - Maxim Integrated Products

Part # MAX128AENG
Description  Multirange, 5V, 12-Bit DAS with 2-Wire Serial Interface
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX128AENG Datasheet(HTML) 5 Page - Maxim Integrated Products

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Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 400kHz;
TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.)
Input Hysteresis
VHYS
0.05 x VDD
V
Input Low Threshold Voltage
VIL
0.3 x VDD
V
Input High Threshold Voltage
VIH
0.7 x VDD
V
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
TIMING CHARACTERISTICS
(VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; TA = TMIN to TMAX;
unless otherwise noted. Typical values are at TA = +25°C.)
Input Capacitance
CIN
15
pF
(Note 4)
Input Leakage Current
IIN
±0.1
±10
µA
VIN = 0 or VDD
Three-State Output Capacitance
COUT
15
pF
(Note 4)
Output Low Voltage
VOL
0.4
V
ISINK = 3mA
2-WIRE FAST MODE
Hold Time (Repeated)
START Condition
tHD,STA
0.6
µs
Bus Free Time Between a
STOP and START Condition
tBUF
1.3
µs
SCL Clock Frequency
fSCL
400
kHz
PARAMETERS
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
Set-Up Time for a Repeated
START Condition
tSU,STA
0.6
µs
High Period of the SCL Clock
tHIGH
0.6
µs
Low Period of the SCL Clock
tLOW
1.3
µs
Rise Time for Both SDA and SCL
Signals (Receiving)
tR
20 +
300
0.1 x Cb
ns
Cb = Total capacitance of one bus line in pF
Data Setup Time
tSU,DAT
100
ns
Data Hold Time
tHD,DAT
0
0.9
µs
DIGITAL INPUTS (SDA, SCL)
DIGITAL OUTPUTS (SDA)
ISINK = 6mA
0.6
Fall Time for Both SDA and SCL
Signals (Receiving)
tF
Cb = Total capacitance of one bus line in pF
20 +
300
0.1 x Cb
ns
Fall Time for Both SDA and SCL
Signals (Transmitting)
tF
Cb = Total capacitance of one bus line in pF
20 +
250
0.1 x Cb
ns
Set-Up Time for STOP Condition
tSU,STO
0.6
µs
Capacitive Load for Each
Bus Line
Cb
400
pF
Pulse Width of Spike Suppressed
tSP
0
50
ns
2-WIRE FAST MODE


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