Electronic Components Datasheet Search |
|
MAX1294BEEI Datasheet(PDF) 11 Page - Maxim Integrated Products |
|
MAX1294BEEI Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 20 page 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface ______________________________________________________________________________________ 11 the acquisition time lengthens and more time must be allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal, and is also the minimum time required for the signal to be acquired. Calculate this with the follow- ing equation: tACQ = 9 (RS + RIN)CIN where RS is the source impedance of the input signal, RIN (800Ω) is the input resistance, and CIN (12pF) is the ADC’s input capacitance. Source impedances below 3k Ω have no significant impact on the MAX1294/ MAX1296’s AC performance. Higher source impedances can be used if a 0.01µF capacitor is connected to the individual analog inputs. Together with the input impedance, this capacitor forms an RC filter, limiting the ADC’s signal bandwidth. Input Bandwidth The MAX1294/MAX1296 T/H stage offers a 350kHz full- linear and a 6MHz full-power bandwidth. This makes it possible to digitize high-speed transients and measure periodic signals with bandwidths exceeding the ADCs sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the fre- quency band of interest, anti-alias filtering is recom- mended. Starting a Conversion Initiate a conversion by writing a control byte, which selects the multiplexer channel and configures the MAX1294/MAX1296 for either unipolar or bipolar opera- tion. A write pulse (WR + CS) can either start an acqui- sition interval or initiate a combined acquisition plus conversion. The sampling interval occurs at the end of the acquisition interval. The ACQMOD (acquisition mode) bit in the input control byte (Table 1) offers two options for acquiring the signal: an internal and an external acquisition. The conversion period lasts for 13 clock cycles in either the internal or external clock or acquisition mode. Writing a new control byte during a conversion cycle will abort the conversion and start a new acquisition interval. Internal Acquisition Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose duration is internally timed. Conversion starts when this acquisition interval (three external clock cycles or approximately 1µs in internal clock mode) ends (Figure 4). Note that when the internal acquisition is combined with the internal clock, the aperture jitter can be as high as 200ps. Internal clock users wishing to achieve the 50ps jitter specification should always use external acquisition mode. External Acquisition Use external acquisition mode for precise control of the sampling aperture and/or dependent control of acquisi- tion and conversion times. The user controls acquisition and start-of-conversion with two separate write pulses. The first pulse, written with ACQMOD = 1, starts an acquisition interval of indeterminate length. The second write pulse, written with ACQMOD = 0 (all other bits in control byte unchanged), terminates acquisition and starts conversion on WR rising edge (Figure 5). The address bits for the input multiplexer must have the same values on the first and second write pulse. Power-down mode bits (PD0, PD1) can assume new values on the second write pulse (see Power-Down Modes section). Changing other bits in the control byte will corrupt the conversion. Reading a Conversion A standard interrupt signal INT is provided to allow the MAX1294/MAX1296 to flag the µP when the conversion has ended and a valid result is available. INT goes low when the conversion is complete and the output data is ready (Figures 4, 5). It returns high on the first read cycle or if a new control byte is written. Selecting Clock Mode The MAX1294/MAX1296 operate with either an internal or an external clock. Control bits D6 and D7 select either internal or external clock mode. The part retains the last requested clock mode if a power-down mode is selected in the current input word. For both internal and external clock mode, internal or external acquisition can be used. At power-up, the MAX1294/MAX1296 enter the default external clock mode. Internal Clock Mode Select internal clock mode to release the µP from the burden of running the SAR conversion clock. Bits D6 and D7 of the control byte must be set to 1; the internal clock frequency is then selected, resulting in a conver- sion time of 3.6µs. When using the internal clock mode, tie the CLK pin either high or low to prevent the pin from floating. |
Similar Part No. - MAX1294BEEI |
|
Similar Description - MAX1294BEEI |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |