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MAX1288 Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX1288 Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 15 page 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 4 _______________________________________________________________________________________ TIMING CHARACTERISTICS (Figures 1, 2, and 5) (VDD = +2.7V to +3.6V, VREF = +2.5V, 0.1µF capacitor at REF, or VDD = +4.75V to +5.25V for MAX1286/MAX1288, VREF = +4.096V, 0.1µF capacitor at REF, fSCLK = 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289. TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25°C.) PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Pulse Width High tCH 38 ns SCLK Pulse Width Low tCL 38 ns SCLK Fall to DOUT Transition tDOT CLOAD = 30pF 60 ns SCLK Rise to DOUT Disable tDOD CLOAD = 30pF 100 500 ns CNVST Rise to DOUT Enable tDOE CLOAD = 30pF 80 ns CNVST Fall to MSB Valid tCONV CLOAD = 30pF 3.7 µs CNVST Pulse Width tCSW 30 ns Note 1: Unipolar mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: Offset nulled. Note 4: The absolute input voltage range for the analog inputs is from GND to VDD. • • • • • • • • • CNVST SCLK DOUT tDOE HIGH-Z HIGH-Z tCSW tCL tCH tDOD tDOT DOUT 6k Ω 6k Ω CL GND DOUT CL GND VDD a) HIGH -Z TO VOH, VOL TO VOH, AND VOH TO HIGH -Z b) HIGH -Z TO VOL, VOH TO VOL, AND VOL TO HIGH -Z Figure 1. Detailed Serial-Interface Timing Sequence Figure 2. Load Circuits for Enable/Disable Times |
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Similar Description - MAX1288 |
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